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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fc1acf317b
Add support for the Image Processing Unit (IPU) found in all Ingenic
SoCs.
The IPU can upscale and downscale a source frame of arbitrary size
ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering
on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can
also be obtained with proper coefficients.
Starting from the JZ4725B, the IPU supports a mode where its output is
sent directly to the LCDC, without having to be written to RAM first.
This makes it possible to use the IPU as a DRM plane on the compatible
SoCs, and have it convert and scale anything the userspace asks for to
what's available for the display.
Regarding pixel formats, older SoCs support packed YUV 4:2:2 and various
planar YUV formats. Newer SoCs introduced support for RGB.
Since the IPU is a separate hardware block, to make it work properly the
Ingenic DRM driver will now register itself as a component master in
case the IPU driver has been enabled in the config.
When enabled in the config, the CRTC will see the IPU as a second primary
plane. It cannot be enabled at the same time as the regular primary
plane. It has the same priority, which means that it will also display
below the overlay plane.
v2: - ingenic-ipu is no longer its own module. It will be built
into the ingenic-drm module.
- If enabled in the config, both the core driver and the IPU
driver will register as components; otherwise the core
driver will bypass that and call the ingenic_drm_bind()
function directly.
- Since both files now build into the same module, the
symbols previously exported as GPL are not exported anymore,
since they are only used internally.
- Fix SPDX license header in ingenic-ipu.h
- Avoid using 'for(;;);' loops without trailing statement(s)
v3: - Pass priv structure to IRQ handler; that way we don't hardcode
the expectation that the IPU plane is at index #0.
- Rework osd_changed() to account for src_* changes
- Add multiplanar YUV 4:4:4 support
- Commit fb addresses to HW at vblank, since addr registers are
not shadow registers
- Probe IPU component later so that IPU plane is last
- Fix driver not working on IPU-less hardware
- Use IPU driver's name as the IRQ name to avoid having two
'ingenic-drm' in /proc/interrupts
- Fix IPU only working for still images on JZ4725B
- Add a bit more code comments
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-10-paul@crapouillou.net
174 lines
5.3 KiB
C
174 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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//
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// Ingenic JZ47xx KMS driver - Register definitions and private API
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//
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// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
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#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
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#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
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#include <linux/bitops.h>
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#include <linux/types.h>
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#define JZ_REG_LCD_CFG 0x00
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#define JZ_REG_LCD_VSYNC 0x04
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#define JZ_REG_LCD_HSYNC 0x08
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#define JZ_REG_LCD_VAT 0x0C
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#define JZ_REG_LCD_DAH 0x10
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#define JZ_REG_LCD_DAV 0x14
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#define JZ_REG_LCD_PS 0x18
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#define JZ_REG_LCD_CLS 0x1C
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#define JZ_REG_LCD_SPL 0x20
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#define JZ_REG_LCD_REV 0x24
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#define JZ_REG_LCD_CTRL 0x30
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#define JZ_REG_LCD_STATE 0x34
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#define JZ_REG_LCD_IID 0x38
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#define JZ_REG_LCD_DA0 0x40
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#define JZ_REG_LCD_SA0 0x44
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#define JZ_REG_LCD_FID0 0x48
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#define JZ_REG_LCD_CMD0 0x4C
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#define JZ_REG_LCD_DA1 0x50
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#define JZ_REG_LCD_SA1 0x54
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#define JZ_REG_LCD_FID1 0x58
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#define JZ_REG_LCD_CMD1 0x5C
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#define JZ_REG_LCD_OSDC 0x100
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#define JZ_REG_LCD_OSDCTRL 0x104
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#define JZ_REG_LCD_OSDS 0x108
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#define JZ_REG_LCD_BGC 0x10c
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#define JZ_REG_LCD_KEY0 0x110
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#define JZ_REG_LCD_KEY1 0x114
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#define JZ_REG_LCD_ALPHA 0x118
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#define JZ_REG_LCD_IPUR 0x11c
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#define JZ_REG_LCD_XYP0 0x120
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#define JZ_REG_LCD_XYP1 0x124
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#define JZ_REG_LCD_SIZE0 0x128
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#define JZ_REG_LCD_SIZE1 0x12c
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#define JZ_LCD_CFG_SLCD BIT(31)
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#define JZ_LCD_CFG_PS_DISABLE BIT(23)
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#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
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#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
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#define JZ_LCD_CFG_REV_DISABLE BIT(20)
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#define JZ_LCD_CFG_HSYNCM BIT(19)
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#define JZ_LCD_CFG_PCLKM BIT(18)
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#define JZ_LCD_CFG_INV BIT(17)
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#define JZ_LCD_CFG_SYNC_DIR BIT(16)
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#define JZ_LCD_CFG_PS_POLARITY BIT(15)
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#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
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#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
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#define JZ_LCD_CFG_REV_POLARITY BIT(12)
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#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
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#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
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#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
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#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
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#define JZ_LCD_CFG_18_BIT BIT(7)
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#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
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#define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
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#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
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#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
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#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
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#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
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#define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
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#define JZ_LCD_CFG_MODE_TV_OUT_P 4
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#define JZ_LCD_CFG_MODE_TV_OUT_I 6
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#define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
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#define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
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#define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
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#define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
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#define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
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#define JZ_LCD_CFG_MODE_LCM 13
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#define JZ_LCD_VSYNC_VPS_OFFSET 16
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#define JZ_LCD_VSYNC_VPE_OFFSET 0
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#define JZ_LCD_HSYNC_HPS_OFFSET 16
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#define JZ_LCD_HSYNC_HPE_OFFSET 0
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#define JZ_LCD_VAT_HT_OFFSET 16
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#define JZ_LCD_VAT_VT_OFFSET 0
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#define JZ_LCD_DAH_HDS_OFFSET 16
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#define JZ_LCD_DAH_HDE_OFFSET 0
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#define JZ_LCD_DAV_VDS_OFFSET 16
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#define JZ_LCD_DAV_VDE_OFFSET 0
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#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
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#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
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#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
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#define JZ_LCD_CTRL_RGB555 BIT(27)
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#define JZ_LCD_CTRL_OFUP BIT(26)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
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#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
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#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
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#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
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#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
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#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
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#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
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#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
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#define JZ_LCD_CTRL_DD_IRQ BIT(8)
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#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
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#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
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#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
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#define JZ_LCD_CTRL_DISABLE BIT(4)
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#define JZ_LCD_CTRL_ENABLE BIT(3)
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#define JZ_LCD_CTRL_BPP_1 0x0
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#define JZ_LCD_CTRL_BPP_2 0x1
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#define JZ_LCD_CTRL_BPP_4 0x2
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#define JZ_LCD_CTRL_BPP_8 0x3
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#define JZ_LCD_CTRL_BPP_15_16 0x4
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#define JZ_LCD_CTRL_BPP_18_24 0x5
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#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)
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#define JZ_LCD_CMD_SOF_IRQ BIT(31)
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#define JZ_LCD_CMD_EOF_IRQ BIT(30)
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#define JZ_LCD_CMD_ENABLE_PAL BIT(28)
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#define JZ_LCD_SYNC_MASK 0x3ff
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#define JZ_LCD_STATE_EOF_IRQ BIT(5)
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#define JZ_LCD_STATE_SOF_IRQ BIT(4)
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#define JZ_LCD_STATE_DISABLED BIT(0)
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#define JZ_LCD_OSDC_OSDEN BIT(0)
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#define JZ_LCD_OSDC_F0EN BIT(3)
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#define JZ_LCD_OSDC_F1EN BIT(4)
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#define JZ_LCD_OSDCTRL_IPU BIT(15)
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#define JZ_LCD_OSDCTRL_RGB555 BIT(4)
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#define JZ_LCD_OSDCTRL_CHANGE BIT(3)
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#define JZ_LCD_OSDCTRL_BPP_15_16 0x4
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#define JZ_LCD_OSDCTRL_BPP_18_24 0x5
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#define JZ_LCD_OSDCTRL_BPP_30 0x7
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#define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7)
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#define JZ_LCD_OSDS_READY BIT(0)
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#define JZ_LCD_IPUR_IPUREN BIT(31)
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#define JZ_LCD_IPUR_IPUR_LSB 0
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#define JZ_LCD_XYP01_XPOS_LSB 0
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#define JZ_LCD_XYP01_YPOS_LSB 16
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#define JZ_LCD_SIZE01_WIDTH_LSB 0
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#define JZ_LCD_SIZE01_HEIGHT_LSB 16
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struct device;
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struct drm_plane;
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struct drm_plane_state;
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struct platform_driver;
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void ingenic_drm_plane_config(struct device *dev,
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struct drm_plane *plane, u32 fourcc);
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void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);
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extern struct platform_driver *ingenic_ipu_driver_ptr;
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#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */
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