Aidan Wood c2ad17c3b2 drm/amd/display: Properly set DCF clock ... [Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for update_bounding_box to be run, and after we run get_maximum_sustainable_clocks we now check if the reported max value of DCF is higher than SOC and if necessary set it to 1000 (becomes 1 after division by 1000) lower than SOC Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:08 -05:00
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acp	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
amdgpu	drm/amdgpu: Enable DC support for Navi10	2019-06-22 09:34:07 -05:00
amdkfd	drm/amdkfd: Add navi10 support to amdkfd. (v3)	2019-06-21 18:59:24 -05:00
display	drm/amd/display: Properly set DCF clock	2019-06-22 09:34:08 -05:00
include	drm/amdgpu/mes10.1: add ip block mes10.1 (v2)	2019-06-21 18:58:22 -05:00
powerplay	drm/amd/powerplay: add interface to get uclk dpm table	2019-06-22 09:34:06 -05:00