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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a3ae549917
On both MT8183 & MT6765, there add "set/clr" register for each clkmux setting, and one update register to trigger value change. It is designed to prevent read-modify-write racing issue. The sw design need to add a new API to handle this hw change with a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h". Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> [sboyd@kernel.org: Squash in flags=0 to silence warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_MUX_H
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#define __DRV_CLK_MTK_MUX_H
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#include <linux/clk-provider.h>
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struct mtk_clk_mux {
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struct clk_hw hw;
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struct regmap *regmap;
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const struct mtk_mux *data;
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spinlock_t *lock;
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};
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struct mtk_mux {
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int id;
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const char *name;
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const char * const *parent_names;
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unsigned int flags;
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u32 mux_ofs;
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u32 set_ofs;
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u32 clr_ofs;
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u32 upd_ofs;
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u8 mux_shift;
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u8 mux_width;
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u8 gate_shift;
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s8 upd_shift;
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const struct clk_ops *ops;
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signed char num_parents;
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};
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extern const struct clk_ops mtk_mux_ops;
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extern const struct clk_ops mtk_mux_clr_set_upd_ops;
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extern const struct clk_ops mtk_mux_gate_ops;
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extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
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#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, _ops) { \
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.id = _id, \
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.name = _name, \
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.mux_ofs = _mux_ofs, \
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.set_ofs = _mux_set_ofs, \
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.clr_ofs = _mux_clr_ofs, \
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.upd_ofs = _upd_ofs, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.gate_shift = _gate, \
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.upd_shift = _upd, \
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.parent_names = _parents, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = _flags, \
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.ops = &_ops, \
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}
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#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags) \
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GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd, _flags, \
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mtk_mux_gate_clr_set_upd_ops)
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#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
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_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
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_gate, _upd_ofs, _upd) \
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MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
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_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
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_width, _gate, _upd_ofs, _upd, \
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CLK_SET_RATE_PARENT)
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struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
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struct regmap *regmap,
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spinlock_t *lock);
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int mtk_clk_register_muxes(const struct mtk_mux *muxes,
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int num, struct device_node *node,
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spinlock_t *lock,
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struct clk_onecell_data *clk_data);
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#endif /* __DRV_CLK_MTK_MUX_H */
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