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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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326b181763
IIR fileter can remove DC offset. It must be enabled when dmic or amic connected to pmic is used. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
510 lines
14 KiB
C
510 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// MediaTek ALSA SoC Audio DAI ADDA Control
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include "mt8183-afe-common.h"
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#include "mt8183-interconnection.h"
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#include "mt8183-reg.h"
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enum {
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AUDIO_SDM_LEVEL_MUTE = 0,
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AUDIO_SDM_LEVEL_NORMAL = 0x1d,
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/* if you change level normal */
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/* you need to change formula of hp impedance and dc trim too */
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};
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enum {
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DELAY_DATA_MISO1 = 0,
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DELAY_DATA_MISO2,
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};
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enum {
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MTK_AFE_ADDA_DL_RATE_8K = 0,
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MTK_AFE_ADDA_DL_RATE_11K = 1,
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MTK_AFE_ADDA_DL_RATE_12K = 2,
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MTK_AFE_ADDA_DL_RATE_16K = 3,
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MTK_AFE_ADDA_DL_RATE_22K = 4,
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MTK_AFE_ADDA_DL_RATE_24K = 5,
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MTK_AFE_ADDA_DL_RATE_32K = 6,
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MTK_AFE_ADDA_DL_RATE_44K = 7,
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MTK_AFE_ADDA_DL_RATE_48K = 8,
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MTK_AFE_ADDA_DL_RATE_96K = 9,
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MTK_AFE_ADDA_DL_RATE_192K = 10,
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};
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enum {
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MTK_AFE_ADDA_UL_RATE_8K = 0,
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MTK_AFE_ADDA_UL_RATE_16K = 1,
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MTK_AFE_ADDA_UL_RATE_32K = 2,
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MTK_AFE_ADDA_UL_RATE_48K = 3,
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MTK_AFE_ADDA_UL_RATE_96K = 4,
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MTK_AFE_ADDA_UL_RATE_192K = 5,
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MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
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};
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static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
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unsigned int rate)
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{
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switch (rate) {
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case 8000:
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return MTK_AFE_ADDA_DL_RATE_8K;
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case 11025:
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return MTK_AFE_ADDA_DL_RATE_11K;
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case 12000:
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return MTK_AFE_ADDA_DL_RATE_12K;
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case 16000:
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return MTK_AFE_ADDA_DL_RATE_16K;
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case 22050:
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return MTK_AFE_ADDA_DL_RATE_22K;
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case 24000:
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return MTK_AFE_ADDA_DL_RATE_24K;
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case 32000:
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return MTK_AFE_ADDA_DL_RATE_32K;
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case 44100:
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return MTK_AFE_ADDA_DL_RATE_44K;
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case 48000:
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return MTK_AFE_ADDA_DL_RATE_48K;
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case 96000:
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return MTK_AFE_ADDA_DL_RATE_96K;
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case 192000:
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return MTK_AFE_ADDA_DL_RATE_192K;
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default:
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dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
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__func__, rate);
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return MTK_AFE_ADDA_DL_RATE_48K;
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}
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}
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static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
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unsigned int rate)
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{
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switch (rate) {
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case 8000:
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return MTK_AFE_ADDA_UL_RATE_8K;
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case 16000:
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return MTK_AFE_ADDA_UL_RATE_16K;
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case 32000:
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return MTK_AFE_ADDA_UL_RATE_32K;
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case 48000:
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return MTK_AFE_ADDA_UL_RATE_48K;
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case 96000:
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return MTK_AFE_ADDA_UL_RATE_96K;
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case 192000:
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return MTK_AFE_ADDA_UL_RATE_192K;
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default:
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dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
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__func__, rate);
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return MTK_AFE_ADDA_UL_RATE_48K;
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}
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}
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/* dai component */
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static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
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I_ADDA_UL_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
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I_ADDA_UL_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
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I_PCM_1_CAP_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
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I_PCM_2_CAP_CH1, 1, 0),
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};
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static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
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I_ADDA_UL_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
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I_ADDA_UL_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
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I_PCM_1_CAP_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
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I_PCM_2_CAP_CH1, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
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I_PCM_1_CAP_CH2, 1, 0),
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SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
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I_PCM_2_CAP_CH2, 1, 0),
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};
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static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol,
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int event)
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{
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struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
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struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
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struct mt8183_afe_private *afe_priv = afe->platform_priv;
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dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
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__func__, w->name, event);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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/* update setting to dmic */
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if (afe_priv->mtkaif_dmic) {
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/* mtkaif_rxif_data_mode = 1, dmic */
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regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
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0x1, 0x1);
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/* dmic mode, 3.25M*/
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regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
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0x0, 0xf << 20);
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
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0x0, 0x1 << 5);
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
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0x0, 0x3 << 14);
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/* turn on dmic, ch1, ch2 */
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
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0x1 << 1, 0x1 << 1);
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regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
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0x3 << 21, 0x3 << 21);
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}
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break;
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case SND_SOC_DAPM_POST_PMD:
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/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
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usleep_range(125, 135);
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break;
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default:
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break;
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}
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return 0;
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}
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/* mtkaif dmic */
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static const char * const mt8183_adda_off_on_str[] = {
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"Off", "On"
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};
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static const struct soc_enum mt8183_adda_enum[] = {
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
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mt8183_adda_off_on_str),
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};
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static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
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struct mt8183_afe_private *afe_priv = afe->platform_priv;
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ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
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return 0;
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}
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static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
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struct mt8183_afe_private *afe_priv = afe->platform_priv;
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struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
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if (ucontrol->value.enumerated.item[0] >= e->items)
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return -EINVAL;
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afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
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dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
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__func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
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return 0;
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}
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static const struct snd_kcontrol_new mtk_adda_controls[] = {
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SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
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mt8183_adda_dmic_get, mt8183_adda_dmic_set),
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};
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enum {
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SUPPLY_SEQ_ADDA_AFE_ON,
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SUPPLY_SEQ_ADDA_DL_ON,
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SUPPLY_SEQ_ADDA_UL_ON,
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};
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static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
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/* adda */
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SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
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mtk_adda_dl_ch1_mix,
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ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
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SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
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mtk_adda_dl_ch2_mix,
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ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
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SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
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AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
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NULL, 0),
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SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
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AFE_ADDA_DL_SRC2_CON0,
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DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
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NULL, 0),
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SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
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AFE_ADDA_UL_SRC_CON0,
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UL_SRC_ON_TMP_CTL_SFT, 0,
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mtk_adda_ul_event,
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SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
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SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
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SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
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SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
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};
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static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
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/* playback */
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{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
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{"ADDA_DL_CH2", "DL1_CH1", "DL1"},
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{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
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{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
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{"ADDA_DL_CH2", "DL2_CH1", "DL2"},
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{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
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{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
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{"ADDA_DL_CH2", "DL3_CH1", "DL3"},
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{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
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{"ADDA Playback", NULL, "ADDA_DL_CH1"},
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{"ADDA Playback", NULL, "ADDA_DL_CH2"},
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/* adda enable */
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{"ADDA Playback", NULL, "ADDA Enable"},
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{"ADDA Playback", NULL, "ADDA Playback Enable"},
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{"ADDA Capture", NULL, "ADDA Enable"},
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{"ADDA Capture", NULL, "ADDA Capture Enable"},
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/* clk */
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{"ADDA Playback", NULL, "mtkaif_26m_clk"},
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{"ADDA Playback", NULL, "aud_dac_clk"},
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{"ADDA Playback", NULL, "aud_dac_predis_clk"},
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{"ADDA Capture", NULL, "mtkaif_26m_clk"},
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{"ADDA Capture", NULL, "aud_adc_clk"},
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};
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static int set_mtkaif_rx(struct mtk_base_afe *afe)
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{
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struct mt8183_afe_private *afe_priv = afe->platform_priv;
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int delay_data;
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int delay_cycle;
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switch (afe_priv->mtkaif_protocol) {
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case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
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regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
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regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
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/* mtkaif_rxif_clkinv_adc inverse for calibration */
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regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
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0x80010000);
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if (afe_priv->mtkaif_phase_cycle[0] >=
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afe_priv->mtkaif_phase_cycle[1]) {
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delay_data = DELAY_DATA_MISO1;
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delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
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afe_priv->mtkaif_phase_cycle[1];
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} else {
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delay_data = DELAY_DATA_MISO2;
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delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
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afe_priv->mtkaif_phase_cycle[0];
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}
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regmap_update_bits(afe->regmap,
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AFE_ADDA_MTKAIF_RX_CFG2,
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MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
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delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
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regmap_update_bits(afe->regmap,
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AFE_ADDA_MTKAIF_RX_CFG2,
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MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
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delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
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break;
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case MT8183_MTKAIF_PROTOCOL_2:
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regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
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regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
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0x00010000);
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break;
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case MT8183_MTKAIF_PROTOCOL_1:
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regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
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regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
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default:
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break;
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}
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return 0;
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}
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/* dai ops */
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static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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unsigned int rate = params_rate(params);
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dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
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__func__, dai->id, substream->stream, rate);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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unsigned int dl_src2_con0 = 0;
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unsigned int dl_src2_con1 = 0;
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/* clean predistortion */
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regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
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regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
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/* set sampling rate */
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dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
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/* set output mode */
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switch (rate) {
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case 192000:
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dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
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dl_src2_con0 |= 1 << 14;
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break;
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case 96000:
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dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
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dl_src2_con0 |= 1 << 14;
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break;
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default:
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dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
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break;
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}
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/* turn off mute function */
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dl_src2_con0 |= (0x03 << 11);
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/* set voice input data if input sample rate is 8k or 16k */
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if (rate == 8000 || rate == 16000)
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dl_src2_con0 |= 0x01 << 5;
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/* SA suggest apply -0.3db to audio/speech path */
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dl_src2_con1 = 0xf74f0000;
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/* turn on down-link gain */
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dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
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regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
|
|
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
|
|
|
|
/* set sdm gain */
|
|
regmap_update_bits(afe->regmap,
|
|
AFE_ADDA_DL_SDM_DCCOMP_CON,
|
|
ATTGAIN_CTL_MASK_SFT,
|
|
AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
|
|
} else {
|
|
unsigned int voice_mode = 0;
|
|
unsigned int ul_src_con0 = 0; /* default value */
|
|
|
|
/* set mtkaif protocol */
|
|
set_mtkaif_rx(afe);
|
|
|
|
/* Using Internal ADC */
|
|
regmap_update_bits(afe->regmap,
|
|
AFE_ADDA_TOP_CON0,
|
|
0x1 << 0,
|
|
0x0 << 0);
|
|
|
|
voice_mode = adda_ul_rate_transform(afe, rate);
|
|
|
|
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
|
|
|
|
/* enable iir */
|
|
ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
|
|
UL_IIR_ON_TMP_CTL_MASK_SFT;
|
|
|
|
/* 35Hz @ 48k */
|
|
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
|
|
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
|
|
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
|
|
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
|
|
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
|
|
|
|
regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
|
|
|
|
/* mtkaif_rxif_data_mode = 0, amic */
|
|
regmap_update_bits(afe->regmap,
|
|
AFE_ADDA_MTKAIF_RX_CFG0,
|
|
0x1 << 0,
|
|
0x0 << 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
|
|
.hw_params = mtk_dai_adda_hw_params,
|
|
};
|
|
|
|
/* dai driver */
|
|
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
|
|
SNDRV_PCM_RATE_96000 |\
|
|
SNDRV_PCM_RATE_192000)
|
|
|
|
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
|
|
SNDRV_PCM_RATE_16000 |\
|
|
SNDRV_PCM_RATE_32000 |\
|
|
SNDRV_PCM_RATE_48000)
|
|
|
|
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
|
|
SNDRV_PCM_FMTBIT_S24_LE |\
|
|
SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
|
|
{
|
|
.name = "ADDA",
|
|
.id = MT8183_DAI_ADDA,
|
|
.playback = {
|
|
.stream_name = "ADDA Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = MTK_ADDA_PLAYBACK_RATES,
|
|
.formats = MTK_ADDA_FORMATS,
|
|
},
|
|
.capture = {
|
|
.stream_name = "ADDA Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = MTK_ADDA_CAPTURE_RATES,
|
|
.formats = MTK_ADDA_FORMATS,
|
|
},
|
|
.ops = &mtk_dai_adda_ops,
|
|
},
|
|
};
|
|
|
|
int mt8183_dai_adda_register(struct mtk_base_afe *afe)
|
|
{
|
|
struct mtk_base_afe_dai *dai;
|
|
|
|
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
|
|
if (!dai)
|
|
return -ENOMEM;
|
|
|
|
list_add(&dai->list, &afe->sub_dais);
|
|
|
|
dai->dai_drivers = mtk_dai_adda_driver;
|
|
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
|
|
|
|
dai->controls = mtk_adda_controls;
|
|
dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
|
|
dai->dapm_widgets = mtk_dai_adda_widgets;
|
|
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
|
|
dai->dapm_routes = mtk_dai_adda_routes;
|
|
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
|
|
return 0;
|
|
}
|