Wenjing Liu c2209d1544 drm/amd/display: Implement DSC MST fair share algorithm ... [why] The current policy will always enable DSC to 12 bpp regardless of if the current bandwidth is enough for MST displays. This logic is not optimal because user will get lower quality output if DSC compression is enabled. This change to is to implement a DSC MST bandwidth fair share algorithm so we will dynamically decide if DSC is needed and what quality (target bpp) is needed to fairly destribute the MST bandwidth in one MST topology. This will allow user to see the most optimal image quality with the given bandwidth. [how] We will start with lowest bandwidth possible and run a Max-Min fairness algorithm to fairly distribute the available bandwidth. If there is still remaining bandwidth, we will try to fit the timing without DSC compression. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:10 -05:00
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amdgpu_dm	drm/amd/display: disable dcn20 abm feature for bring up	2019-06-22 09:34:08 -05:00
dc	drm/amd/display: Implement DSC MST fair share algorithm	2019-06-22 09:34:10 -05:00
include	drm/amd/display: Add DSC support for Navi (v2)	2019-06-22 09:34:07 -05:00
modules	drm/amd/display: Add 3dlut control flags	2019-06-22 09:34:09 -05:00
Kconfig	drm/amd/display: enable DSC support by default	2019-06-22 09:34:08 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00