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Code logic is similar with arithmetic right shift by constant, and NFP get indirect shift amount through source A operand of PREV_ALU. It is possible to fall back to logic right shift if the MSB is known to be zero from range info, however there is no benefit to do this given logic indirect right shift use the same number and cycle of instruction sequence. Suppose the MSB of regX is the bit we want to replicate to fill in all the vacant positions, and regY contains the shift amount, then we could use single instruction to set up both. [alu, --, regY, OR, regX] -- NOTE: the PREV_ALU result doesn't need to write to any destination register. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> |
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3com | ||
8390 | ||
adaptec | ||
aeroflex | ||
agere | ||
alacritech | ||
allwinner | ||
alteon | ||
altera | ||
amazon | ||
amd | ||
apm | ||
apple | ||
aquantia | ||
arc | ||
atheros | ||
aurora | ||
broadcom | ||
brocade | ||
cadence | ||
calxeda | ||
cavium | ||
chelsio | ||
cirrus | ||
cisco | ||
cortina | ||
davicom | ||
dec | ||
dlink | ||
emulex | ||
ezchip | ||
faraday | ||
freescale | ||
fujitsu | ||
hisilicon | ||
hp | ||
huawei | ||
i825xx | ||
ibm | ||
intel | ||
marvell | ||
mediatek | ||
mellanox | ||
micrel | ||
microchip | ||
moxa | ||
mscc | ||
myricom | ||
natsemi | ||
neterion | ||
netronome | ||
ni | ||
nuvoton | ||
nvidia | ||
nxp | ||
oki-semi | ||
packetengines | ||
pasemi | ||
qlogic | ||
qualcomm | ||
rdc | ||
realtek | ||
renesas | ||
rocker | ||
samsung | ||
seeq | ||
sfc | ||
sgi | ||
silan | ||
sis | ||
smsc | ||
socionext | ||
stmicro | ||
sun | ||
synopsys | ||
tehuti | ||
ti | ||
toshiba | ||
tundra | ||
via | ||
wiznet | ||
xilinx | ||
xircom | ||
xscale | ||
dnet.c | ||
dnet.h | ||
ec_bhf.c | ||
ethoc.c | ||
fealnx.c | ||
jme.c | ||
jme.h | ||
Kconfig | ||
korina.c | ||
lantiq_etop.c | ||
Makefile | ||
netx-eth.c |