mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 08:26:53 +07:00
c2ce6f9f3d
As our various loops (copy, string, crypto etc) get more complicated, we want to share implementations between userspace (eg glibc) and the kernel. We also want to write userspace test harnesses to put in tools/testing/selftest. One gratuitous difference between userspace and the kernel is the VMX register definitions - the kernel uses vrX whereas both gcc and glibc use vX. Change the kernel to match userspace. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
657 lines
11 KiB
ArmAsm
657 lines
11 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#include <asm/ppc_asm.h>
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_GLOBAL(memcpy_power7)
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#ifdef __BIG_ENDIAN__
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#define LVS(VRT,RA,RB) lvsl VRT,RA,RB
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#define VPERM(VRT,VRA,VRB,VRC) vperm VRT,VRA,VRB,VRC
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#else
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#define LVS(VRT,RA,RB) lvsr VRT,RA,RB
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#define VPERM(VRT,VRA,VRB,VRC) vperm VRT,VRB,VRA,VRC
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#endif
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#ifdef CONFIG_ALTIVEC
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cmpldi r5,16
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cmpldi cr1,r5,4096
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std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
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blt .Lshort_copy
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bgt cr1,.Lvmx_copy
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#else
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cmpldi r5,16
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std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
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blt .Lshort_copy
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#endif
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.Lnonvmx_copy:
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/* Get the source 8B aligned */
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neg r6,r4
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mtocrf 0x01,r6
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clrldi r6,r6,(64-3)
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bf cr7*4+3,1f
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lbz r0,0(r4)
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addi r4,r4,1
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stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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3: sub r5,r5,r6
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cmpldi r5,128
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blt 5f
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mflr r0
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stdu r1,-STACKFRAMESIZE(r1)
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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std r17,STK_REG(R17)(r1)
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std r18,STK_REG(R18)(r1)
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std r19,STK_REG(R19)(r1)
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std r20,STK_REG(R20)(r1)
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std r21,STK_REG(R21)(r1)
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std r22,STK_REG(R22)(r1)
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std r0,STACKFRAMESIZE+16(r1)
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srdi r6,r5,7
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mtctr r6
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/* Now do cacheline (128B) sized loads and stores. */
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.align 5
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4:
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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ld r9,32(r4)
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ld r10,40(r4)
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ld r11,48(r4)
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ld r12,56(r4)
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ld r14,64(r4)
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ld r15,72(r4)
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ld r16,80(r4)
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ld r17,88(r4)
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ld r18,96(r4)
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ld r19,104(r4)
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ld r20,112(r4)
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ld r21,120(r4)
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addi r4,r4,128
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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std r9,32(r3)
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std r10,40(r3)
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std r11,48(r3)
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std r12,56(r3)
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std r14,64(r3)
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std r15,72(r3)
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std r16,80(r3)
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std r17,88(r3)
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std r18,96(r3)
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std r19,104(r3)
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std r20,112(r3)
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std r21,120(r3)
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addi r3,r3,128
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bdnz 4b
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clrldi r5,r5,(64-7)
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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ld r17,STK_REG(R17)(r1)
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ld r18,STK_REG(R18)(r1)
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ld r19,STK_REG(R19)(r1)
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ld r20,STK_REG(R20)(r1)
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ld r21,STK_REG(R21)(r1)
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ld r22,STK_REG(R22)(r1)
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addi r1,r1,STACKFRAMESIZE
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/* Up to 127B to go */
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5: srdi r6,r5,4
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mtocrf 0x01,r6
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6: bf cr7*4+1,7f
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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ld r9,32(r4)
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ld r10,40(r4)
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ld r11,48(r4)
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ld r12,56(r4)
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addi r4,r4,64
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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std r9,32(r3)
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std r10,40(r3)
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std r11,48(r3)
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std r12,56(r3)
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addi r3,r3,64
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/* Up to 63B to go */
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7: bf cr7*4+2,8f
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ld r0,0(r4)
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ld r6,8(r4)
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ld r7,16(r4)
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ld r8,24(r4)
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addi r4,r4,32
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std r0,0(r3)
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std r6,8(r3)
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std r7,16(r3)
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std r8,24(r3)
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addi r3,r3,32
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/* Up to 31B to go */
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8: bf cr7*4+3,9f
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ld r0,0(r4)
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ld r6,8(r4)
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addi r4,r4,16
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std r0,0(r3)
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std r6,8(r3)
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addi r3,r3,16
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9: clrldi r5,r5,(64-4)
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/* Up to 15B to go */
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.Lshort_copy:
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mtocrf 0x01,r5
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bf cr7*4+0,12f
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lwz r0,0(r4) /* Less chance of a reject with word ops */
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lwz r6,4(r4)
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addi r4,r4,8
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stw r0,0(r3)
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stw r6,4(r3)
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addi r3,r3,8
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12: bf cr7*4+1,13f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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13: bf cr7*4+2,14f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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14: bf cr7*4+3,15f
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lbz r0,0(r4)
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stb r0,0(r3)
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15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
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blr
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.Lunwind_stack_nonvmx_copy:
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addi r1,r1,STACKFRAMESIZE
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b .Lnonvmx_copy
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#ifdef CONFIG_ALTIVEC
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.Lvmx_copy:
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mflr r0
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std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
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std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
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std r0,16(r1)
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stdu r1,-STACKFRAMESIZE(r1)
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bl enter_vmx_copy
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cmpwi cr1,r3,0
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ld r0,STACKFRAMESIZE+16(r1)
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ld r3,STK_REG(R31)(r1)
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ld r4,STK_REG(R30)(r1)
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ld r5,STK_REG(R29)(r1)
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mtlr r0
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/*
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* We prefetch both the source and destination using enhanced touch
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* instructions. We use a stream ID of 0 for the load side and
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* 1 for the store side.
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*/
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clrrdi r6,r4,7
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clrrdi r9,r3,7
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ori r9,r9,1 /* stream=1 */
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srdi r7,r5,7 /* length in cachelines, capped at 0x3FF */
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cmpldi r7,0x3FF
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ble 1f
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li r7,0x3FF
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1: lis r0,0x0E00 /* depth=7 */
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sldi r7,r7,7
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or r7,r7,r0
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ori r10,r7,1 /* stream=1 */
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lis r8,0x8000 /* GO=1 */
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clrldi r8,r8,32
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.machine push
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.machine "power4"
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dcbt r0,r6,0b01000
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dcbt r0,r7,0b01010
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dcbtst r0,r9,0b01000
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dcbtst r0,r10,0b01010
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eieio
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dcbt r0,r8,0b01010 /* GO */
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.machine pop
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beq cr1,.Lunwind_stack_nonvmx_copy
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/*
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* If source and destination are not relatively aligned we use a
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* slower permute loop.
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*/
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xor r6,r4,r3
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rldicl. r6,r6,0,(64-4)
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bne .Lvmx_unaligned_copy
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/* Get the destination 16B aligned */
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neg r6,r3
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mtocrf 0x01,r6
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clrldi r6,r6,(64-4)
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bf cr7*4+3,1f
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lbz r0,0(r4)
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addi r4,r4,1
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stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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3: bf cr7*4+0,4f
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ld r0,0(r4)
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addi r4,r4,8
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std r0,0(r3)
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addi r3,r3,8
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4: sub r5,r5,r6
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/* Get the desination 128B aligned */
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neg r6,r3
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srdi r7,r6,4
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mtocrf 0x01,r7
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clrldi r6,r6,(64-7)
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li r9,16
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li r10,32
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li r11,48
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bf cr7*4+3,5f
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lvx v1,r0,r4
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addi r4,r4,16
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stvx v1,r0,r3
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addi r3,r3,16
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5: bf cr7*4+2,6f
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lvx v1,r0,r4
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lvx v0,r4,r9
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addi r4,r4,32
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stvx v1,r0,r3
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stvx v0,r3,r9
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addi r3,r3,32
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6: bf cr7*4+1,7f
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lvx v3,r0,r4
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lvx v2,r4,r9
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lvx v1,r4,r10
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lvx v0,r4,r11
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addi r4,r4,64
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stvx v3,r0,r3
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stvx v2,r3,r9
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stvx v1,r3,r10
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stvx v0,r3,r11
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addi r3,r3,64
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7: sub r5,r5,r6
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srdi r6,r5,7
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std r14,STK_REG(R14)(r1)
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std r15,STK_REG(R15)(r1)
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std r16,STK_REG(R16)(r1)
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li r12,64
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li r14,80
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li r15,96
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li r16,112
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mtctr r6
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/*
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* Now do cacheline sized loads and stores. By this stage the
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* cacheline stores are also cacheline aligned.
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*/
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.align 5
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8:
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lvx v7,r0,r4
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lvx v6,r4,r9
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lvx v5,r4,r10
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lvx v4,r4,r11
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lvx v3,r4,r12
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lvx v2,r4,r14
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lvx v1,r4,r15
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lvx v0,r4,r16
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addi r4,r4,128
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stvx v7,r0,r3
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stvx v6,r3,r9
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stvx v5,r3,r10
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stvx v4,r3,r11
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stvx v3,r3,r12
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stvx v2,r3,r14
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stvx v1,r3,r15
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stvx v0,r3,r16
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addi r3,r3,128
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bdnz 8b
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ld r14,STK_REG(R14)(r1)
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ld r15,STK_REG(R15)(r1)
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ld r16,STK_REG(R16)(r1)
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/* Up to 127B to go */
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clrldi r5,r5,(64-7)
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srdi r6,r5,4
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mtocrf 0x01,r6
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bf cr7*4+1,9f
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lvx v3,r0,r4
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lvx v2,r4,r9
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lvx v1,r4,r10
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lvx v0,r4,r11
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addi r4,r4,64
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stvx v3,r0,r3
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stvx v2,r3,r9
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stvx v1,r3,r10
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stvx v0,r3,r11
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addi r3,r3,64
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9: bf cr7*4+2,10f
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lvx v1,r0,r4
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lvx v0,r4,r9
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addi r4,r4,32
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stvx v1,r0,r3
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stvx v0,r3,r9
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addi r3,r3,32
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10: bf cr7*4+3,11f
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lvx v1,r0,r4
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addi r4,r4,16
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stvx v1,r0,r3
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addi r3,r3,16
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/* Up to 15B to go */
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11: clrldi r5,r5,(64-4)
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mtocrf 0x01,r5
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bf cr7*4+0,12f
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ld r0,0(r4)
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addi r4,r4,8
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std r0,0(r3)
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addi r3,r3,8
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12: bf cr7*4+1,13f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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13: bf cr7*4+2,14f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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14: bf cr7*4+3,15f
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lbz r0,0(r4)
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stb r0,0(r3)
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15: addi r1,r1,STACKFRAMESIZE
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ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
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b exit_vmx_copy /* tail call optimise */
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.Lvmx_unaligned_copy:
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/* Get the destination 16B aligned */
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neg r6,r3
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mtocrf 0x01,r6
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clrldi r6,r6,(64-4)
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bf cr7*4+3,1f
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lbz r0,0(r4)
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addi r4,r4,1
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stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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lhz r0,0(r4)
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addi r4,r4,2
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sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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lwz r0,0(r4)
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addi r4,r4,4
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stw r0,0(r3)
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addi r3,r3,4
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3: bf cr7*4+0,4f
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lwz r0,0(r4) /* Less chance of a reject with word ops */
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lwz r7,4(r4)
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addi r4,r4,8
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stw r0,0(r3)
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stw r7,4(r3)
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addi r3,r3,8
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4: sub r5,r5,r6
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/* Get the desination 128B aligned */
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neg r6,r3
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srdi r7,r6,4
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mtocrf 0x01,r7
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clrldi r6,r6,(64-7)
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|
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li r9,16
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li r10,32
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li r11,48
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LVS(v16,0,r4) /* Setup permute control vector */
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lvx v0,0,r4
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addi r4,r4,16
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bf cr7*4+3,5f
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lvx v1,r0,r4
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VPERM(v8,v0,v1,v16)
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addi r4,r4,16
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stvx v8,r0,r3
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addi r3,r3,16
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vor v0,v1,v1
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|
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5: bf cr7*4+2,6f
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lvx v1,r0,r4
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VPERM(v8,v0,v1,v16)
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lvx v0,r4,r9
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VPERM(v9,v1,v0,v16)
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|
addi r4,r4,32
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|
stvx v8,r0,r3
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stvx v9,r3,r9
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addi r3,r3,32
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|
|
|
6: bf cr7*4+1,7f
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lvx v3,r0,r4
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VPERM(v8,v0,v3,v16)
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|
lvx v2,r4,r9
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|
VPERM(v9,v3,v2,v16)
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|
lvx v1,r4,r10
|
|
VPERM(v10,v2,v1,v16)
|
|
lvx v0,r4,r11
|
|
VPERM(v11,v1,v0,v16)
|
|
addi r4,r4,64
|
|
stvx v8,r0,r3
|
|
stvx v9,r3,r9
|
|
stvx v10,r3,r10
|
|
stvx v11,r3,r11
|
|
addi r3,r3,64
|
|
|
|
7: sub r5,r5,r6
|
|
srdi r6,r5,7
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|
|
|
std r14,STK_REG(R14)(r1)
|
|
std r15,STK_REG(R15)(r1)
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|
std r16,STK_REG(R16)(r1)
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|
|
|
li r12,64
|
|
li r14,80
|
|
li r15,96
|
|
li r16,112
|
|
|
|
mtctr r6
|
|
|
|
/*
|
|
* Now do cacheline sized loads and stores. By this stage the
|
|
* cacheline stores are also cacheline aligned.
|
|
*/
|
|
.align 5
|
|
8:
|
|
lvx v7,r0,r4
|
|
VPERM(v8,v0,v7,v16)
|
|
lvx v6,r4,r9
|
|
VPERM(v9,v7,v6,v16)
|
|
lvx v5,r4,r10
|
|
VPERM(v10,v6,v5,v16)
|
|
lvx v4,r4,r11
|
|
VPERM(v11,v5,v4,v16)
|
|
lvx v3,r4,r12
|
|
VPERM(v12,v4,v3,v16)
|
|
lvx v2,r4,r14
|
|
VPERM(v13,v3,v2,v16)
|
|
lvx v1,r4,r15
|
|
VPERM(v14,v2,v1,v16)
|
|
lvx v0,r4,r16
|
|
VPERM(v15,v1,v0,v16)
|
|
addi r4,r4,128
|
|
stvx v8,r0,r3
|
|
stvx v9,r3,r9
|
|
stvx v10,r3,r10
|
|
stvx v11,r3,r11
|
|
stvx v12,r3,r12
|
|
stvx v13,r3,r14
|
|
stvx v14,r3,r15
|
|
stvx v15,r3,r16
|
|
addi r3,r3,128
|
|
bdnz 8b
|
|
|
|
ld r14,STK_REG(R14)(r1)
|
|
ld r15,STK_REG(R15)(r1)
|
|
ld r16,STK_REG(R16)(r1)
|
|
|
|
/* Up to 127B to go */
|
|
clrldi r5,r5,(64-7)
|
|
srdi r6,r5,4
|
|
mtocrf 0x01,r6
|
|
|
|
bf cr7*4+1,9f
|
|
lvx v3,r0,r4
|
|
VPERM(v8,v0,v3,v16)
|
|
lvx v2,r4,r9
|
|
VPERM(v9,v3,v2,v16)
|
|
lvx v1,r4,r10
|
|
VPERM(v10,v2,v1,v16)
|
|
lvx v0,r4,r11
|
|
VPERM(v11,v1,v0,v16)
|
|
addi r4,r4,64
|
|
stvx v8,r0,r3
|
|
stvx v9,r3,r9
|
|
stvx v10,r3,r10
|
|
stvx v11,r3,r11
|
|
addi r3,r3,64
|
|
|
|
9: bf cr7*4+2,10f
|
|
lvx v1,r0,r4
|
|
VPERM(v8,v0,v1,v16)
|
|
lvx v0,r4,r9
|
|
VPERM(v9,v1,v0,v16)
|
|
addi r4,r4,32
|
|
stvx v8,r0,r3
|
|
stvx v9,r3,r9
|
|
addi r3,r3,32
|
|
|
|
10: bf cr7*4+3,11f
|
|
lvx v1,r0,r4
|
|
VPERM(v8,v0,v1,v16)
|
|
addi r4,r4,16
|
|
stvx v8,r0,r3
|
|
addi r3,r3,16
|
|
|
|
/* Up to 15B to go */
|
|
11: clrldi r5,r5,(64-4)
|
|
addi r4,r4,-16 /* Unwind the +16 load offset */
|
|
mtocrf 0x01,r5
|
|
bf cr7*4+0,12f
|
|
lwz r0,0(r4) /* Less chance of a reject with word ops */
|
|
lwz r6,4(r4)
|
|
addi r4,r4,8
|
|
stw r0,0(r3)
|
|
stw r6,4(r3)
|
|
addi r3,r3,8
|
|
|
|
12: bf cr7*4+1,13f
|
|
lwz r0,0(r4)
|
|
addi r4,r4,4
|
|
stw r0,0(r3)
|
|
addi r3,r3,4
|
|
|
|
13: bf cr7*4+2,14f
|
|
lhz r0,0(r4)
|
|
addi r4,r4,2
|
|
sth r0,0(r3)
|
|
addi r3,r3,2
|
|
|
|
14: bf cr7*4+3,15f
|
|
lbz r0,0(r4)
|
|
stb r0,0(r3)
|
|
|
|
15: addi r1,r1,STACKFRAMESIZE
|
|
ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
|
|
b exit_vmx_copy /* tail call optimise */
|
|
#endif /* CONFIG_ALTIVEC */
|