mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
86614b5d6d
Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock. These clocks were erroneously provided by the clock and reset controller and are now provided by the PMC instead because that's where the primary controls are. This patch adds #clock-cells property with 1 clock specifier to the Tegra PMC node in device tree. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
1049 lines
29 KiB
Plaintext
1049 lines
29 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/tegra30-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra30-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/tegra-pmc.h>
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/ {
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compatible = "nvidia,tegra30";
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interrupt-parent = <&lic>;
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#address-cells = <1>;
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#size-cells = <1>;
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x0>;
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};
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pcie@3000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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0x00003800 0x00000200 /* AFI registers */
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0x10000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
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0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
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clocks = <&tegra_car TEGRA30_CLK_PCIE>,
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<&tegra_car TEGRA30_CLK_AFI>,
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<&tegra_car TEGRA30_CLK_PLL_E>,
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<&tegra_car TEGRA30_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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bus-range = <0x00 0xff>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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bus-range = <0x00 0xff>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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bus-range = <0x00 0xff>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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iram@40000000 {
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compatible = "mmio-sram";
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reg = <0x40000000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40000000 0x40000>;
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vde_pool: vde@400 {
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reg = <0x400 0x3fc00>;
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pool;
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};
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};
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host1x@50000000 {
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compatible = "nvidia,tegra30-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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iommus = <&mc TEGRA_SWGROUP_HC>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe@54040000 {
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compatible = "nvidia,tegra30-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_MPE>;
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resets = <&tegra_car 60>;
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reset-names = "mpe";
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iommus = <&mc TEGRA_SWGROUP_MPE>;
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};
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vi@54080000 {
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compatible = "nvidia,tegra30-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_VI>;
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resets = <&tegra_car 20>;
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reset-names = "vi";
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iommus = <&mc TEGRA_SWGROUP_VI>;
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};
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epp@540c0000 {
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compatible = "nvidia,tegra30-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_EPP>;
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resets = <&tegra_car 19>;
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reset-names = "epp";
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iommus = <&mc TEGRA_SWGROUP_EPP>;
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};
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isp@54100000 {
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compatible = "nvidia,tegra30-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_ISP>;
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resets = <&tegra_car 23>;
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reset-names = "isp";
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iommus = <&mc TEGRA_SWGROUP_ISP>;
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};
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gr2d@54140000 {
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compatible = "nvidia,tegra30-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_GR2D>;
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resets = <&tegra_car 21>;
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reset-names = "2d";
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iommus = <&mc TEGRA_SWGROUP_G2>;
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};
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gr3d@54180000 {
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compatible = "nvidia,tegra30-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car TEGRA30_CLK_GR3D
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&tegra_car TEGRA30_CLK_GR3D2>;
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clock-names = "3d", "3d2";
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resets = <&tegra_car 24>,
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<&tegra_car 98>;
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reset-names = "3d", "3d2";
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iommus = <&mc TEGRA_SWGROUP_NV>,
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<&mc TEGRA_SWGROUP_NV2>;
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};
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dc@54200000 {
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compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_DISP1>,
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<&tegra_car TEGRA30_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DC>;
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nvidia,head = <0>;
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra30-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_DISP2>,
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<&tegra_car TEGRA30_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DCB>;
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nvidia,head = <1>;
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rgb {
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status = "disabled";
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};
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};
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hdmi@54280000 {
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compatible = "nvidia,tegra30-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_HDMI>,
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<&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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status = "disabled";
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};
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tvo@542c0000 {
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compatible = "nvidia,tegra30-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_TVO>;
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status = "disabled";
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};
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dsi@54300000 {
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compatible = "nvidia,tegra30-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA30_CLK_DSIA>;
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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status = "disabled";
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};
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};
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timer@50040600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x50040600 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&tegra_car TEGRA30_CLK_TWD>;
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};
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intc: interrupt-controller@50041000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x50041000 0x1000
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0x50040100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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};
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cache-controller@50043000 {
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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arm,data-latency = <6 6 2>;
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arm,tag-latency = <5 5 2>;
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cache-unified;
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cache-level = <2>;
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};
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lic: interrupt-controller@60004000 {
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compatible = "nvidia,tegra30-ictlr";
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reg = <0x60004000 0x100>,
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<0x60004100 0x50>,
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<0x60004200 0x50>,
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<0x60004300 0x50>,
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<0x60004400 0x50>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_TIMER>;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra30-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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flow-controller@60007000 {
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compatible = "nvidia,tegra30-flowctrl";
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reg = <0x60007000 0x1000>;
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};
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apbdma: dma@6000a000 {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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ahb: ahb@6000c000 {
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compatible = "nvidia,tegra30-ahb";
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reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
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};
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actmon@6000c800 {
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compatible = "nvidia,tegra30-actmon";
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reg = <0x6000c800 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
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<&tegra_car TEGRA30_CLK_EMC>;
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clock-names = "actmon", "emc";
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resets = <&tegra_car TEGRA30_CLK_ACTMON>;
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reset-names = "actmon";
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/*
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gpio-ranges = <&pinmux 0 0 248>;
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*/
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};
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vde@6001a000 {
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compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
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reg = <0x6001a000 0x1000 /* Syntax Engine */
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0x6001b000 0x1000 /* Video Bitstream Engine */
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0x6001c000 0x100 /* Macroblock Engine */
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0x6001c200 0x100 /* Post-processing Engine */
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0x6001c400 0x100 /* Motion Compensation Engine */
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0x6001c600 0x100 /* Transform Engine */
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0x6001c800 0x100 /* Pixel prediction block */
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0x6001ca00 0x100 /* Video DMA */
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0x6001d800 0x400>; /* Video frame controls */
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reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
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"tfe", "ppb", "vdma", "frameid";
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iram = <&vde_pool>; /* IRAM region */
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
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interrupt-names = "sync-token", "bsev", "sxe";
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clocks = <&tegra_car TEGRA30_CLK_VDE>;
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reset-names = "vde", "mc";
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resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
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iommus = <&mc TEGRA_SWGROUP_VDE>;
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};
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apbmisc@70000800 {
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compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
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reg = <0x70000800 0x64 /* Chip revision */
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0x70000008 0x04>; /* Strapping options */
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};
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pinmux: pinmux@70000868 {
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compatible = "nvidia,tegra30-pinmux";
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reg = <0x70000868 0xd4 /* Pad control registers */
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0x70003000 0x3e4>; /* Mux registers */
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};
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|
|
/*
|
|
* There are two serial driver i.e. 8250 based simple serial
|
|
* driver and APB DMA based serial driver for higher baudrate
|
|
* and performace. To enable the 8250 based driver, the compatible
|
|
* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
|
|
* the APB DMA based serial driver, the compatible is
|
|
* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
|
|
*/
|
|
uarta: serial@70006000 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_UARTA>;
|
|
resets = <&tegra_car 6>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 8>, <&apbdma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartb: serial@70006040 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006040 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_UARTB>;
|
|
resets = <&tegra_car 7>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 9>, <&apbdma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@70006200 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_UARTC>;
|
|
resets = <&tegra_car 55>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 10>, <&apbdma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartd: serial@70006300 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_UARTD>;
|
|
resets = <&tegra_car 65>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 19>, <&apbdma 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uarte: serial@70006400 {
|
|
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
|
|
reg = <0x70006400 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_UARTE>;
|
|
resets = <&tegra_car 66>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 20>, <&apbdma 20>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmi@70009000 {
|
|
compatible = "nvidia,tegra30-gmi";
|
|
reg = <0x70009000 0x1000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x48000000 0x7ffffff>;
|
|
clocks = <&tegra_car TEGRA30_CLK_NOR>;
|
|
clock-names = "gmi";
|
|
resets = <&tegra_car 42>;
|
|
reset-names = "gmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@7000a000 {
|
|
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
|
|
reg = <0x7000a000 0x100>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&tegra_car TEGRA30_CLK_PWM>;
|
|
resets = <&tegra_car 17>;
|
|
reset-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@7000e000 {
|
|
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
|
reg = <0x7000e000 0x100>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_RTC>;
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c000 0x100>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2C1>,
|
|
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
resets = <&tegra_car 12>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 21>, <&apbdma 21>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c400 0x100>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2C2>,
|
|
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
resets = <&tegra_car 54>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 22>, <&apbdma 22>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c500 0x100>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2C3>,
|
|
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
resets = <&tegra_car 67>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 23>, <&apbdma 23>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c700 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000c700 0x100>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2C4>,
|
|
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
|
|
resets = <&tegra_car 103>;
|
|
reset-names = "i2c";
|
|
clock-names = "div-clk", "fast-clk";
|
|
dmas = <&apbdma 26>, <&apbdma 26>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
|
reg = <0x7000d000 0x100>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2C5>,
|
|
<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
resets = <&tegra_car 47>;
|
|
reset-names = "i2c";
|
|
dmas = <&apbdma 24>, <&apbdma 24>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d400 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d400 0x200>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC1>;
|
|
resets = <&tegra_car 41>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 15>, <&apbdma 15>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d600 0x200>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC2>;
|
|
resets = <&tegra_car 44>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 16>, <&apbdma 16>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000d800 0x200>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC3>;
|
|
resets = <&tegra_car 46>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 17>, <&apbdma 17>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000da00 0x200>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC4>;
|
|
resets = <&tegra_car 68>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 18>, <&apbdma 18>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000dc00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000dc00 0x200>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC5>;
|
|
resets = <&tegra_car 104>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 27>, <&apbdma 27>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000de00 {
|
|
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
|
reg = <0x7000de00 0x200>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SBC6>;
|
|
resets = <&tegra_car 106>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 28>, <&apbdma 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
kbc@7000e200 {
|
|
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
|
|
reg = <0x7000e200 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_KBC>;
|
|
resets = <&tegra_car 36>;
|
|
reset-names = "kbc";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_pmc: pmc@7000e400 {
|
|
compatible = "nvidia,tegra30-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mc: memory-controller@7000f000 {
|
|
compatible = "nvidia,tegra30-mc";
|
|
reg = <0x7000f000 0x400>;
|
|
clocks = <&tegra_car TEGRA30_CLK_MC>;
|
|
clock-names = "mc";
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#iommu-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
memory-controller@7000f400 {
|
|
compatible = "nvidia,tegra30-emc";
|
|
reg = <0x7000f400 0x400>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_EMC>;
|
|
|
|
nvidia,memory-controller = <&mc>;
|
|
};
|
|
|
|
fuse@7000f800 {
|
|
compatible = "nvidia,tegra30-efuse";
|
|
reg = <0x7000f800 0x400>;
|
|
clocks = <&tegra_car TEGRA30_CLK_FUSE>;
|
|
clock-names = "fuse";
|
|
resets = <&tegra_car 39>;
|
|
reset-names = "fuse";
|
|
};
|
|
|
|
hda@70030000 {
|
|
compatible = "nvidia,tegra30-hda";
|
|
reg = <0x70030000 0x10000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_HDA>,
|
|
<&tegra_car TEGRA30_CLK_HDA2HDMI>,
|
|
<&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
|
|
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
resets = <&tegra_car 125>, /* hda */
|
|
<&tegra_car 128>, /* hda2hdmi */
|
|
<&tegra_car 111>; /* hda2codec_2x */
|
|
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
status = "disabled";
|
|
};
|
|
|
|
ahub@70080000 {
|
|
compatible = "nvidia,tegra30-ahub";
|
|
reg = <0x70080000 0x200
|
|
0x70080200 0x100>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
|
|
<&tegra_car TEGRA30_CLK_APBIF>;
|
|
clock-names = "d_audio", "apbif";
|
|
resets = <&tegra_car 106>, /* d_audio */
|
|
<&tegra_car 107>, /* apbif */
|
|
<&tegra_car 30>, /* i2s0 */
|
|
<&tegra_car 11>, /* i2s1 */
|
|
<&tegra_car 18>, /* i2s2 */
|
|
<&tegra_car 101>, /* i2s3 */
|
|
<&tegra_car 102>, /* i2s4 */
|
|
<&tegra_car 108>, /* dam0 */
|
|
<&tegra_car 109>, /* dam1 */
|
|
<&tegra_car 110>, /* dam2 */
|
|
<&tegra_car 10>; /* spdif */
|
|
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
|
"spdif";
|
|
dmas = <&apbdma 1>, <&apbdma 1>,
|
|
<&apbdma 2>, <&apbdma 2>,
|
|
<&apbdma 3>, <&apbdma 3>,
|
|
<&apbdma 4>, <&apbdma 4>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
|
"rx3", "tx3";
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
tegra_i2s0: i2s@70080300 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080300 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S0>;
|
|
resets = <&tegra_car 30>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70080400 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080400 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S1>;
|
|
resets = <&tegra_car 11>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70080500 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080500 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S2>;
|
|
resets = <&tegra_car 18>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70080600 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080600 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S3>;
|
|
resets = <&tegra_car 101>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70080700 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080700 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S4>;
|
|
resets = <&tegra_car 102>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
|
|
resets = <&tegra_car 14>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
|
|
resets = <&tegra_car 9>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
|
|
resets = <&tegra_car 69>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
|
|
resets = <&tegra_car 15>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d000000 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USBD>;
|
|
resets = <&tegra_car 22>;
|
|
reset-names = "usb";
|
|
nvidia,needs-double-reset;
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@7d000000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USBD>,
|
|
<&tegra_car TEGRA30_CLK_PLL_U>,
|
|
<&tegra_car TEGRA30_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 22>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <9>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <51>;
|
|
nvidia,xcvr-setup-use-fuses;
|
|
nvidia,xcvr-lsfslew = <1>;
|
|
nvidia,xcvr-lsrslew = <1>;
|
|
nvidia,xcvr-hsslew = <32>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,has-utmi-pad-registers;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d004000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d004000 0x4000>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USB2>;
|
|
resets = <&tegra_car 58>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy2: usb-phy@7d004000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USB2>,
|
|
<&tegra_car TEGRA30_CLK_PLL_U>,
|
|
<&tegra_car TEGRA30_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 58>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <9>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <51>;
|
|
nvidia,xcvr-setup-use-fuses;
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
nvidia,xcvr-lsrslew = <2>;
|
|
nvidia,xcvr-hsslew = <32>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d008000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d008000 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USB3>;
|
|
resets = <&tegra_car 59>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy3: usb-phy@7d008000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA30_CLK_USB3>,
|
|
<&tegra_car TEGRA30_CLK_PLL_U>,
|
|
<&tegra_car TEGRA30_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 59>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <51>;
|
|
nvidia,xcvr-setup-use-fuses;
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
nvidia,xcvr-lsrslew = <2>;
|
|
nvidia,xcvr-hsslew = <32>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <2>;
|
|
clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <3>;
|
|
clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&{/cpus/cpu@0}>,
|
|
<&{/cpus/cpu@1}>,
|
|
<&{/cpus/cpu@2}>,
|
|
<&{/cpus/cpu@3}>;
|
|
};
|
|
};
|