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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f3286a3af8
The initial driver support was for a single mPIPE shim on the chip (as is the case for the Gx36 hardware). The Gx72 chip has two mPIPE shims, so we extend the driver to handle that case. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
606 lines
23 KiB
C
606 lines
23 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/**
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* Interface definitions for the mpipe driver.
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*/
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#ifndef _SYS_HV_DRV_MPIPE_INTF_H
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#define _SYS_HV_DRV_MPIPE_INTF_H
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#include <arch/mpipe.h>
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#include <arch/mpipe_constants.h>
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/** Number of mPIPE instances supported */
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#define HV_MPIPE_INSTANCE_MAX (2)
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/** Number of buffer stacks (32). */
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#define HV_MPIPE_NUM_BUFFER_STACKS \
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(MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH)
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/** Number of NotifRings (256). */
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#define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS)
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/** Number of NotifGroups (32). */
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#define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS)
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/** Number of buckets (4160). */
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#define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS)
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/** Number of "lo" buckets (4096). */
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#define HV_MPIPE_NUM_LO_BUCKETS 4096
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/** Number of "hi" buckets (64). */
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#define HV_MPIPE_NUM_HI_BUCKETS \
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(HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS)
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/** Number of edma rings (24). */
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#define HV_MPIPE_NUM_EDMA_RINGS \
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(MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH)
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/** A flag bit indicating a fixed resource allocation. */
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#define HV_MPIPE_ALLOC_FIXED 0x01
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/** Offset for the config register MMIO region. */
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#define HV_MPIPE_CONFIG_MMIO_OFFSET \
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(MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT)
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/** Size of the config register MMIO region. */
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#define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024)
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/** Offset for the config register MMIO region. */
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#define HV_MPIPE_FAST_MMIO_OFFSET \
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(MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT)
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/** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */
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#define HV_MPIPE_FAST_MMIO_SIZE \
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((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \
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<< MPIPE_MMIO_ADDR__REGION_SHIFT)
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/*
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* Each type of resource allocation comes in quantized chunks, where
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* XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number
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* of resources in each chunk.
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*/
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/** Number of buffer stack chunks available (32). */
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#define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \
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MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH
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/** Granularity of buffer stack allocation (1). */
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#define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \
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(HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS)
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/** Number of NotifRing chunks available (32). */
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#define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \
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MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH
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/** Granularity of NotifRing allocation (8). */
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#define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \
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(HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS)
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/** Number of NotifGroup chunks available (32). */
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#define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \
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HV_MPIPE_NUM_NOTIF_GROUPS
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/** Granularity of NotifGroup allocation (1). */
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#define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \
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(HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS)
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/** Number of lo bucket chunks available (16). */
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#define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \
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MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH
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/** Granularity of lo bucket allocation (256). */
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#define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \
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(HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS)
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/** Number of hi bucket chunks available (16). */
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#define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \
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MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH
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/** Granularity of hi bucket allocation (4). */
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#define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \
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(HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS)
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/** Number of eDMA ring chunks available (24). */
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#define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \
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MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH
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/** Granularity of eDMA ring allocation (1). */
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#define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \
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(HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS)
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/** Bit vector encoding which NotifRings are in a NotifGroup. */
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typedef struct
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{
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/** The actual bits. */
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uint64_t ring_mask[4];
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} gxio_mpipe_notif_group_bits_t;
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/** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */
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typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t;
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/** Eight buffer stack ids. */
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typedef struct
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{
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/** The stacks. */
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uint8_t stacks[8];
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} gxio_mpipe_rules_stacks_t;
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/** A destination mac address. */
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typedef struct
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{
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/** The octets. */
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uint8_t octets[6];
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} gxio_mpipe_rules_dmac_t;
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/** A vlan. */
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typedef uint16_t gxio_mpipe_rules_vlan_t;
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/** Maximum number of characters in a link name. */
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#define GXIO_MPIPE_LINK_NAME_LEN 32
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/** Structure holding a link name. Only needed, and only typedef'ed,
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* because the IORPC stub generator only handles types which are single
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* words coming before the parameter name. */
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typedef struct
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{
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/** The name itself. */
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char name[GXIO_MPIPE_LINK_NAME_LEN];
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}
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_gxio_mpipe_link_name_t;
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/** Maximum number of characters in a symbol name. */
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#define GXIO_MPIPE_SYMBOL_NAME_LEN 128
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/** Structure holding a symbol name. Only needed, and only typedef'ed,
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* because the IORPC stub generator only handles types which are single
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* words coming before the parameter name. */
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typedef struct
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{
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/** The name itself. */
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char name[GXIO_MPIPE_SYMBOL_NAME_LEN];
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}
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_gxio_mpipe_symbol_name_t;
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/** Structure holding a MAC address. */
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typedef struct
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{
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/** The address. */
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uint8_t mac[6];
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}
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_gxio_mpipe_link_mac_t;
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/** Request shared data permission -- that is, the ability to send and
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* receive packets -- on the specified link. Other processes may also
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* request shared data permission on the same link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
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* or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
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*/
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#define GXIO_MPIPE_LINK_DATA 0x00000001UL
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/** Do not request data permission on the specified link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
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* or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
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*/
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#define GXIO_MPIPE_LINK_NO_DATA 0x00000002UL
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/** Request exclusive data permission -- that is, the ability to send and
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* receive packets -- on the specified link. No other processes may
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* request data permission on this link, and if any process already has
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* data permission on it, this open will fail.
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*
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* No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
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* or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
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*/
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#define GXIO_MPIPE_LINK_EXCL_DATA 0x00000004UL
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/** Request shared stats permission -- that is, the ability to read and write
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* registers which contain link statistics, and to get link attributes --
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* on the specified link. Other processes may also request shared stats
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* permission on the same link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
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* or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
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*/
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#define GXIO_MPIPE_LINK_STATS 0x00000008UL
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/** Do not request stats permission on the specified link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
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* or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
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*/
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#define GXIO_MPIPE_LINK_NO_STATS 0x00000010UL
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/** Request exclusive stats permission -- that is, the ability to read and
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* write registers which contain link statistics, and to get link
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* attributes -- on the specified link. No other processes may request
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* stats permission on this link, and if any process already
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* has stats permission on it, this open will fail.
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*
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* Requesting exclusive stats permission is normally a very bad idea, since
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* it prevents programs like mpipe-stat from providing information on this
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* link. Applications should only do this if they use MAC statistics
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* registers, and cannot tolerate any of the clear-on-read registers being
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* reset by other statistics programs.
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*
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* No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
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* or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
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*/
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#define GXIO_MPIPE_LINK_EXCL_STATS 0x00000020UL
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/** Request shared control permission -- that is, the ability to modify link
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* attributes, and read and write MAC and MDIO registers -- on the
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* specified link. Other processes may also request shared control
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* permission on the same link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
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* or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
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*/
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#define GXIO_MPIPE_LINK_CTL 0x00000040UL
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/** Do not request control permission on the specified link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
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* or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
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*/
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#define GXIO_MPIPE_LINK_NO_CTL 0x00000080UL
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/** Request exclusive control permission -- that is, the ability to modify
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* link attributes, and read and write MAC and MDIO registers -- on the
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* specified link. No other processes may request control permission on
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* this link, and if any process already has control permission on it,
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* this open will fail.
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*
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* Requesting exclusive control permission is not always a good idea, since
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* it prevents programs like mpipe-link from configuring the link.
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*
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* No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
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* or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
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*/
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#define GXIO_MPIPE_LINK_EXCL_CTL 0x00000100UL
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/** Set the desired state of the link to up, allowing any speeds which are
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* supported by the link hardware, as part of this open operation; do not
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* change the desired state of the link when it is closed or the process
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* exits. No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
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* ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
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* ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
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*/
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#define GXIO_MPIPE_LINK_AUTO_UP 0x00000200UL
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/** Set the desired state of the link to up, allowing any speeds which are
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* supported by the link hardware, as part of this open operation; when the
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* link is closed or this process exits, if no other process has the link
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* open, set the desired state of the link to down. No more than one of
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* ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
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* ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
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* specifed in a gxio_mpipe_link_open() call. If none are specified,
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* ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
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*/
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#define GXIO_MPIPE_LINK_AUTO_UPDOWN 0x00000400UL
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/** Do not change the desired state of the link as part of the open
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* operation; when the link is closed or this process exits, if no other
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* process has the link open, set the desired state of the link to down.
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* No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
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* ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
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* ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
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* call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
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*/
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#define GXIO_MPIPE_LINK_AUTO_DOWN 0x00000800UL
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/** Do not change the desired state of the link as part of the open
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* operation; do not change the desired state of the link when it is
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* closed or the process exits. No more than one of
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* ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
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* ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
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* specifed in a gxio_mpipe_link_open() call. If none are specified,
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* ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
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*/
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#define GXIO_MPIPE_LINK_AUTO_NONE 0x00001000UL
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/** Request that this open call not complete until the network link is up.
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* The process will wait as long as necessary for this to happen;
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* applications which wish to abandon waiting for the link after a
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* specific time period should not specify this flag when opening a link,
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* but should instead call gxio_mpipe_link_wait() afterward. The link
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* must be opened with stats permission. Note that this flag by itself
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* does not change the desired link state; if other open flags or previous
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* link state changes have not requested a desired state of up, the open
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* call will never complete. This flag is not available to kernel
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* clients.
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*/
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#define GXIO_MPIPE_LINK_WAIT 0x00002000UL
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/*
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* Note: link attributes must fit in 24 bits, since we use the top 8 bits
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* of the IORPC offset word for the channel number.
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*/
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/** Determine whether jumbo frames may be received. If this attribute's
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* value value is nonzero, the MAC will accept frames of up to 10240 bytes.
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* If the value is zero, the MAC will only accept frames of up to 1544
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* bytes. The default value is zero. */
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#define GXIO_MPIPE_LINK_RECEIVE_JUMBO 0x010000
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/** Determine whether to send pause frames on this link if the mPIPE packet
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* FIFO is nearly full. If the value is zero, pause frames are not sent.
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* If the value is nonzero, it is the delay value which will be sent in any
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* pause frames which are output, in units of 512 bit times.
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*
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* Bear in mind that in almost all circumstances, the mPIPE packet FIFO
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* will never fill up, since mPIPE will empty it as fast as or faster than
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* the incoming data rate, by either delivering or dropping packets. The
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* only situation in which this is not true is if the memory and cache
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* subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of
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* packet data to memory in a timely fashion. In particular, pause frames
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* will <em>not</em> be sent if packets cannot be delivered because
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* NotifRings are full, buckets are full, or buffers are not available in
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* a buffer stack. */
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#define GXIO_MPIPE_LINK_SEND_PAUSE 0x020000
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/** Determine whether to suspend output on the receipt of pause frames.
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* If the value is nonzero, mPIPE shim will suspend output on the link's
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* channel when a pause frame is received. If the value is zero, pause
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* frames will be ignored. The default value is zero. */
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#define GXIO_MPIPE_LINK_RECEIVE_PAUSE 0x030000
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/** Interface MAC address. The value is a 6-byte MAC address, in the least
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* significant 48 bits of the value; in other words, an address which would
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* be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would
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* be returned as 0x12345678ab.
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*
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* Depending upon the overall system design, a MAC address may or may not
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* be available for each interface. Note that the interface's MAC address
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* does not limit the packets received on its channel, although the
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* classifier's rules could be configured to do that. Similarly, the MAC
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* address is not used when transmitting packets, although applications
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* could certainly decide to use the assigned address as a source MAC
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* address when doing so. This attribute may only be retrieved with
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* gxio_mpipe_link_get_attr(); it may not be modified.
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*/
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#define GXIO_MPIPE_LINK_MAC 0x040000
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/** Determine whether to discard egress packets on link down. If this value
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* is nonzero, packets sent on this link while the link is down will be
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* discarded. If this value is zero, no packets will be sent on this link
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* while it is down. The default value is one. */
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#define GXIO_MPIPE_LINK_DISCARD_IF_DOWN 0x050000
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/** Possible link state. The value is a combination of link state flags,
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* ORed together, that indicate link modes which are actually supported by
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* the hardware. This attribute may only be retrieved with
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* gxio_mpipe_link_get_attr(); it may not be modified. */
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#define GXIO_MPIPE_LINK_POSSIBLE_STATE 0x060000
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/** Current link state. The value is a combination of link state flags,
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* ORed together, that indicate the current state of the hardware. If the
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* link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero;
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* if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will
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* result in exactly one of the speed values, indicating the current speed.
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* This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it
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* may not be modified. */
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#define GXIO_MPIPE_LINK_CURRENT_STATE 0x070000
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/** Desired link state. The value is a conbination of flags, which specify
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* the desired state for the link. With gxio_mpipe_link_set_attr(), this
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* will, in the background, attempt to bring up the link using whichever of
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* the requested flags are reasonable, or take down the link if the flags
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* are zero. The actual link up or down operation may happen after this
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* call completes. If the link state changes in the future, the system
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* will continue to try to get back to the desired link state; for
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* instance, if the link is brought up successfully, and then the network
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* cable is disconnected, the link will go down. However, the desired
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* state of the link is still up, so if the cable is reconnected, the link
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* will be brought up again.
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*
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* With gxio_mpipe_link_set_attr(), this will indicate the desired state
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* for the link, as set with a previous gxio_mpipe_link_set_attr() call,
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* or implicitly by a gxio_mpipe_link_open() or link close operation.
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* This may not reflect the current state of the link; to get that, use
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* ::GXIO_MPIPE_LINK_CURRENT_STATE.
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*/
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#define GXIO_MPIPE_LINK_DESIRED_STATE 0x080000
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/** Link can run, should run, or is running at 10 Mbps. */
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#define GXIO_MPIPE_LINK_10M 0x0000000000000001UL
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/** Link can run, should run, or is running at 100 Mbps. */
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#define GXIO_MPIPE_LINK_100M 0x0000000000000002UL
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/** Link can run, should run, or is running at 1 Gbps. */
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#define GXIO_MPIPE_LINK_1G 0x0000000000000004UL
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/** Link can run, should run, or is running at 10 Gbps. */
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#define GXIO_MPIPE_LINK_10G 0x0000000000000008UL
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/** Link can run, should run, or is running at 20 Gbps. */
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#define GXIO_MPIPE_LINK_20G 0x0000000000000010UL
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/** Link can run, should run, or is running at 25 Gbps. */
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#define GXIO_MPIPE_LINK_25G 0x0000000000000020UL
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/** Link can run, should run, or is running at 50 Gbps. */
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#define GXIO_MPIPE_LINK_50G 0x0000000000000040UL
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|
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/** Link should run at the highest speed supported by the link and by
|
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* the device connected to the link. Only usable as a value for
|
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* the link's desired state; never returned as a value for the current
|
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* or possible states. */
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#define GXIO_MPIPE_LINK_ANYSPEED 0x0000000000000800UL
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|
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/** All legal link speeds. This value is provided for use in extracting
|
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* the speed-related subset of the link state flags; it is not intended
|
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* to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE
|
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* attributes. A link is up or is requested to be up if its current or
|
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* desired state, respectively, ANDED with this value, is nonzero. */
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#define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL
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|
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/** Link can run, should run, or is running in MAC loopback mode. This
|
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* loops transmitted packets back to the receiver, inside the Tile
|
|
* Processor. */
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#define GXIO_MPIPE_LINK_LOOP_MAC 0x0000000000001000UL
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/** Link can run, should run, or is running in PHY loopback mode. This
|
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* loops transmitted packets back to the receiver, inside the external
|
|
* PHY chip. */
|
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#define GXIO_MPIPE_LINK_LOOP_PHY 0x0000000000002000UL
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/** Link can run, should run, or is running in external loopback mode.
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* This requires that an external loopback plug be installed on the
|
|
* Ethernet port. Note that only some links require that this be
|
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* configured via the gxio_mpipe_link routines; other links can do
|
|
* external loopack with the plug and no special configuration. */
|
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#define GXIO_MPIPE_LINK_LOOP_EXT 0x0000000000004000UL
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|
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/** All legal loopback types. */
|
|
#define GXIO_MPIPE_LINK_LOOP_MASK 0x000000000000F000UL
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|
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/** Link can run, should run, or is running in full-duplex mode.
|
|
* If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
|
|
* specified in a set of desired state flags, both are assumed. */
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|
#define GXIO_MPIPE_LINK_FDX 0x0000000000010000UL
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|
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/** Link can run, should run, or is running in half-duplex mode.
|
|
* If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
|
|
* specified in a set of desired state flags, both are assumed. */
|
|
#define GXIO_MPIPE_LINK_HDX 0x0000000000020000UL
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|
|
|
|
|
/** An individual rule. */
|
|
typedef struct
|
|
{
|
|
/** The total size. */
|
|
uint16_t size;
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|
|
/** The priority. */
|
|
int16_t priority;
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|
|
|
/** The "headroom" in each buffer. */
|
|
uint8_t headroom;
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|
|
|
/** The "tailroom" in each buffer. */
|
|
uint8_t tailroom;
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|
|
|
/** The "capacity" of the largest buffer. */
|
|
uint16_t capacity;
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|
|
|
/** The mask for converting a flow hash into a bucket. */
|
|
uint16_t bucket_mask;
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|
|
|
/** The offset for converting a flow hash into a bucket. */
|
|
uint16_t bucket_first;
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|
|
/** The buffer stack ids. */
|
|
gxio_mpipe_rules_stacks_t stacks;
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|
|
/** The actual channels. */
|
|
uint32_t channel_bits;
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|
|
|
/** The number of dmacs. */
|
|
uint16_t num_dmacs;
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|
|
|
/** The number of vlans. */
|
|
uint16_t num_vlans;
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|
|
|
/** The actual dmacs and vlans. */
|
|
uint8_t dmacs_and_vlans[];
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|
|
|
} gxio_mpipe_rules_rule_t;
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|
|
|
|
|
/** A list of classifier rules. */
|
|
typedef struct
|
|
{
|
|
/** The offset to the end of the current rule. */
|
|
uint16_t tail;
|
|
|
|
/** The offset to the start of the current rule. */
|
|
uint16_t head;
|
|
|
|
/** The actual rules. */
|
|
uint8_t rules[4096 - 4];
|
|
|
|
} gxio_mpipe_rules_list_t;
|
|
|
|
|
|
|
|
|
|
/** mPIPE statistics structure. These counters include all relevant
|
|
* events occurring on all links within the mPIPE shim. */
|
|
typedef struct
|
|
{
|
|
/** Number of ingress packets dropped for any reason. */
|
|
uint64_t ingress_drops;
|
|
/** Number of ingress packets dropped because a buffer stack was empty. */
|
|
uint64_t ingress_drops_no_buf;
|
|
/** Number of ingress packets dropped or truncated due to lack of space in
|
|
* the iPkt buffer. */
|
|
uint64_t ingress_drops_ipkt;
|
|
/** Number of ingress packets dropped by the classifier or load balancer */
|
|
uint64_t ingress_drops_cls_lb;
|
|
/** Total number of ingress packets. */
|
|
uint64_t ingress_packets;
|
|
/** Total number of egress packets. */
|
|
uint64_t egress_packets;
|
|
/** Total number of ingress bytes. */
|
|
uint64_t ingress_bytes;
|
|
/** Total number of egress bytes. */
|
|
uint64_t egress_bytes;
|
|
}
|
|
gxio_mpipe_stats_t;
|
|
|
|
|
|
#endif /* _SYS_HV_DRV_MPIPE_INTF_H */
|