linux_dsm_epyc7002/drivers/clk/meson
Jerome Brunet c178b003bf clk: meson: remove special gp0 lock loop
After testing, it appears that the gxl (and axg) does not require the
special locking/reset loop which was initially added for it.

All the values present in the gxl table can locked with the simple lock
checking loop.

The change switches the gxl and axg gp0 back to the simple lock checking
loop and removes the code no longer required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:38 +01:00
..
axg.c clk: meson: remove special gp0 lock loop 2018-03-13 10:09:38 +01:00
axg.h clk: meson: split divider and gate part of mpll 2018-03-13 10:04:03 +01:00
clk-audio-divider.c clk: meson: migrate the audio divider clock to clk_regmap 2018-03-13 10:04:02 +01:00
clk-mpll.c clk: meson: split divider and gate part of mpll 2018-03-13 10:04:03 +01:00
clk-pll.c clk: meson: remove special gp0 lock loop 2018-03-13 10:09:38 +01:00
clk-regmap.c clk: meson: add regmap clocks 2018-03-13 10:03:58 +01:00
clk-regmap.h clk: meson: add regmap clocks 2018-03-13 10:03:58 +01:00
clkc.h clk: meson: remove special gp0 lock loop 2018-03-13 10:09:38 +01:00
gxbb-aoclk-32k.c clk: meson: gxbb-aoclk: Add CEC 32k clock 2017-08-04 18:02:02 +02:00
gxbb-aoclk.c clk: meson: switch gxbb ao_clk to clk_regmap 2018-03-13 10:03:59 +01:00
gxbb-aoclk.h clk: meson: remove superseded aoclk_gate_regmap 2018-03-13 10:03:59 +01:00
gxbb.c clk: meson: remove special gp0 lock loop 2018-03-13 10:09:38 +01:00
gxbb.h clk: meson: split divider and gate part of mpll 2018-03-13 10:04:03 +01:00
Kconfig clk: meson: use hhi syscon if available 2018-03-13 10:04:04 +01:00
Makefile clk: meson: remove obsolete cpu_clk 2018-03-13 10:04:04 +01:00
meson8b.c clk: meson: add fractional part of meson8b fixed_pll 2018-03-13 10:09:33 +01:00
meson8b.h clk: meson: rework meson8b cpu clock 2018-03-13 10:04:03 +01:00