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198a72c8f9
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. Add the optional ocmem property to the Adreno Graphics Management Unit bindings. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
117 lines
3.0 KiB
Plaintext
117 lines
3.0 KiB
Plaintext
Qualcomm adreno/snapdragon GMU (Graphics management unit)
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The GMU is a programmable power controller for the GPU. the CPU controls the
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GMU which in turn handles power controls for the GPU.
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Required properties:
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- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
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for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
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Note that you need to list the less specific "qcom,adreno-gmu"
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for generic matches and the more specific identifier to identify
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the specific device.
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- reg: Physical base address and length of the GMU registers.
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- reg-names: Matching names for the register regions
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* "gmu"
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* "gmu_pdc"
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* "gmu_pdc_seg"
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- interrupts: The interrupt signals from the GMU.
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- interrupt-names: Matching names for the interrupts
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* "hfi"
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* "gmu"
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- clocks: phandles to the device clocks
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- clock-names: Matching names for the clocks
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* "gmu"
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* "cxo"
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* "axi"
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* "mnoc"
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- power-domains: should be:
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<&clock_gpucc GPU_CX_GDSC>
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<&clock_gpucc GPU_GX_GDSC>
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- power-domain-names: Matching names for the power domains
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- iommus: phandle to the adreno iommu
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- operating-points-v2: phandle to the OPP operating points
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Optional properties:
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- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
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SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
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Example:
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/ {
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...
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0x506a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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};
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};
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a3xx example with OCMEM support:
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/ {
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...
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gpu: adreno@fdb00000 {
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compatible = "qcom,adreno-330.2",
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"qcom,adreno";
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reg = <0xfdb00000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clock-names = "core",
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"iface",
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"mem_iface";
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clocks = <&mmcc OXILI_GFX3D_CLK>,
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<&mmcc OXILICX_AHB_CLK>,
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<&mmcc OXILICX_AXI_CLK>;
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sram = <&gmu_sram>;
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power-domains = <&mmcc OXILICX_GDSC>;
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operating-points-v2 = <&gpu_opp_table>;
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iommus = <&gpu_iommu 0>;
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};
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ocmem@fdd00000 {
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compatible = "qcom,msm8974-ocmem";
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reg = <0xfdd00000 0x2000>,
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<0xfec00000 0x180000>;
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reg-names = "ctrl",
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"mem";
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clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
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<&mmcc OCMEMCX_OCMEMNOC_CLK>;
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clock-names = "core",
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"iface";
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#address-cells = <1>;
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#size-cells = <1>;
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gmu_sram: gmu-sram@0 {
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reg = <0x0 0x100000>;
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ranges = <0 0 0xfec00000 0x100000>;
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};
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};
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};
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