mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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62e59c4e69
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "ccu_phase.h"
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static int ccu_phase_get_phase(struct clk_hw *hw)
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{
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struct ccu_phase *phase = hw_to_ccu_phase(hw);
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struct clk_hw *parent, *grandparent;
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unsigned int parent_rate, grandparent_rate;
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u16 step, parent_div;
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u32 reg;
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u8 delay;
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reg = readl(phase->common.base + phase->common.reg);
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delay = (reg >> phase->shift);
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delay &= (1 << phase->width) - 1;
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if (!delay)
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return 180;
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/* Get our parent clock, it's the one that can adjust its rate */
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parent = clk_hw_get_parent(hw);
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if (!parent)
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return -EINVAL;
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/* And its rate */
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parent_rate = clk_hw_get_rate(parent);
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if (!parent_rate)
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return -EINVAL;
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/* Now, get our parent's parent (most likely some PLL) */
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grandparent = clk_hw_get_parent(parent);
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if (!grandparent)
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return -EINVAL;
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/* And its rate */
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grandparent_rate = clk_hw_get_rate(grandparent);
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if (!grandparent_rate)
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return -EINVAL;
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/* Get our parent clock divider */
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parent_div = grandparent_rate / parent_rate;
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step = DIV_ROUND_CLOSEST(360, parent_div);
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return delay * step;
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}
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static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
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{
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struct ccu_phase *phase = hw_to_ccu_phase(hw);
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struct clk_hw *parent, *grandparent;
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unsigned int parent_rate, grandparent_rate;
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unsigned long flags;
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u32 reg;
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u8 delay;
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/* Get our parent clock, it's the one that can adjust its rate */
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parent = clk_hw_get_parent(hw);
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if (!parent)
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return -EINVAL;
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/* And its rate */
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parent_rate = clk_hw_get_rate(parent);
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if (!parent_rate)
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return -EINVAL;
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/* Now, get our parent's parent (most likely some PLL) */
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grandparent = clk_hw_get_parent(parent);
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if (!grandparent)
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return -EINVAL;
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/* And its rate */
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grandparent_rate = clk_hw_get_rate(grandparent);
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if (!grandparent_rate)
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return -EINVAL;
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if (degrees != 180) {
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u16 step, parent_div;
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/* Get our parent divider */
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parent_div = grandparent_rate / parent_rate;
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/*
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* We can only outphase the clocks by multiple of the
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* PLL's period.
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*
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* Since our parent clock is only a divider, and the
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* formula to get the outphasing in degrees is deg =
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* 360 * delta / period
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*
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* If we simplify this formula, we can see that the
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* only thing that we're concerned about is the number
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* of period we want to outphase our clock from, and
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* the divider set by our parent clock.
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*/
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step = DIV_ROUND_CLOSEST(360, parent_div);
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delay = DIV_ROUND_CLOSEST(degrees, step);
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} else {
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delay = 0;
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}
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spin_lock_irqsave(phase->common.lock, flags);
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reg = readl(phase->common.base + phase->common.reg);
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reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
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writel(reg | (delay << phase->shift),
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phase->common.base + phase->common.reg);
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spin_unlock_irqrestore(phase->common.lock, flags);
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return 0;
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}
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const struct clk_ops ccu_phase_ops = {
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.get_phase = ccu_phase_get_phase,
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.set_phase = ccu_phase_set_phase,
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};
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