Stephen Boyd 5816b74581 Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next ... - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs - Support for Cirrus Logic Lochnagar clks * clk-hisi: clk: hi3660: Mark clk_gate_ufs_subsys as critical * clk-lochnagar: clk: lochnagar: Add support for the Cirrus Logic Lochnagar clk: lochnagar: Add initial binding documentation * clk-allwinner: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate * clk-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328 * clk-qoriq: clk: qoriq: increase array size of cmux_to_group dt-bindings: qoriq-clock: Add ls1028a chip compatible string clk: qoriq: Add ls1028a clock configuration clk: qoriq: add more PLL divider clocks support dt-bindings: qoriq-clock: add more PLL divider clocks support		2019-05-07 11:45:13 -07:00
..
clk-cpu.c	clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()	2017-09-28 15:22:50 +02:00
clk-ddr.c	clk: core: replace clk_{readl,writel} with {readl,writel}	2019-04-23 10:57:49 -07:00
clk-half-divider.c	clk: core: replace clk_{readl,writel} with {readl,writel}	2019-04-23 10:57:49 -07:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Fix error return in phase clock registration	2018-03-23 09:08:43 +01:00
clk-muxgrf.c	clk: rockchip: add a clock-type for muxes based in the grf	2017-01-02 14:24:57 +01:00
clk-pll.c	clk: rockchip: add pll_wait_lock for pll_enable	2017-03-22 18:33:22 +01:00
clk-px30.c	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
clk-rk3036.c	clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036	2017-06-02 15:42:38 +02:00
clk-rk3128.c	clk: rockchip: add sclk_timer5 as critical clock on rk3128	2017-09-17 01:55:36 +02:00
clk-rk3188.c	clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks	2019-01-07 09:17:15 +01:00
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-03-23 08:49:35 +01:00
clk-rk3288.c	clk: rockchip: undo several noc and special clocks as critical on rk3288	2019-04-23 12:17:11 +02:00
clk-rk3328.c	clk: rockchip: fix wrong clock definitions for rk3328	2019-03-18 08:45:55 +01:00
clk-rk3368.c	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	2017-10-14 21:31:58 +02:00
clk-rk3399.c	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399	2018-08-06 23:46:52 +02:00
clk-rv1108.c	clk: rockchip: fix the rv1108 clk_mac sel register description	2017-08-22 02:55:03 +02:00
clk.c	clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type	2019-04-12 22:34:18 +02:00
clk.h	clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type	2019-04-12 22:34:18 +02:00
Makefile	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00