mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 12:46:41 +07:00
12afc0cf81
The default is enabled, and there should be no need to reconfigure the status for SoC internal devices in the board specific files. Only the USB PHY used needs to be configured in the board specific files. Cc: Bin Liu <b-liu@ti.com> Cc: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
576 lines
14 KiB
Plaintext
576 lines
14 KiB
Plaintext
/*
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* pdu001.dts
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*
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* EETS GmbH PDU001 board device tree file
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*
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* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/leds-pca9532.h>
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/ {
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model = "EETS,PDU001";
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compatible = "ti,am33xx";
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chosen {
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stdout-path = &uart3;
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};
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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vbat: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vbat";
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regulator-min-microvolt = <3600000>;
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regulator-max-microvolt = <3600000>;
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regulator-boot-on;
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};
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lis3_reg: fixedregulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "lis3_reg";
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regulator-boot-on;
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};
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panel {
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compatible = "ti,tilcdc,panel";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins_s0>;
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panel-info {
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ac-bias = <255>;
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ac-bias-intrpt = <0>;
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dma-burst-sz = <16>;
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bpp = <16>;
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fdd = <0x80>;
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sync-edge = <0>;
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sync-ctrl = <1>;
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raster-order = <0>;
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fifo-th = <0>;
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};
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display-timings {
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240x320p16 {
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clock-frequency = <6500000>;
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hactive = <240>;
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vactive = <320>;
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hfront-porch = <6>;
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hback-porch = <6>;
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hsync-len = <1>;
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vback-porch = <6>;
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vfront-porch = <6>;
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vsync-len = <1>;
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hsync-active = <0>;
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vsync-active = <0>;
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pixelclk-active = <1>;
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de-active = <0>;
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};
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};
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};
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&clkout2_pin>;
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
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>;
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};
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i2c2_pins: pinmux_i2c2_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */
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AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */
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>;
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};
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spi1_pins: pinmux_spi1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
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AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
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AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
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AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)
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AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */
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AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
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>;
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};
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clkout2_pin: pinmux_clkout2_pin {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Port 1 (emac0) */
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AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)
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/* Port 2 (emac1) */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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/* eMMC */
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
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>;
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};
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mmc2_pins: pinmux_mmc2_pins {
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/* SD cardcage */
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
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/* card change signal for frontpanel SD cardcage */
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AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
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>;
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};
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lcd_pins_s0: lcd_pins_s0 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
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>;
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};
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dcan0_pins: pinmux_dcan0_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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rs485-rts-active-high;
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rs485-rts-delay = <0 0>;
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linux,rs485-enabled-at-boot-time;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <400000>;
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tps: tps@2d {
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reg = <0x2d>;
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};
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m2_eeprom: m2_eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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status = "okay";
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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clock-frequency = <100000>;
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board_24aa025e48: board_24aa025e48@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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backplane_24aa025e48: backplane_24aa025e48@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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};
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pca9532: pca9532@60 {
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compatible = "nxp,pca9532";
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reg = <0x60>;
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psc0 = <0x97>;
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pwm0 = <0x80>;
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psc1 = <0x97>;
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pwm1 = <0x10>;
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run.red@0 {
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type = <PCA9532_TYPE_LED>;
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};
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run.green@1 {
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type = <PCA9532_TYPE_LED>;
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default-state = "on";
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};
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s2.red@2 {
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type = <PCA9532_TYPE_LED>;
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};
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s2.green@3 {
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type = <PCA9532_TYPE_LED>;
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};
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s1.yellow@4 {
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type = <PCA9532_TYPE_LED>;
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};
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s1.green@5 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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pca9530: pca9530@61 {
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compatible = "nxp,pca9530";
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reg = <0x61>;
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tft-panel@0 {
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type = <PCA9532_TYPE_LED>;
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linux,default-trigger = "backlight";
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default-state = "on";
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};
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};
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mcp79400: mcp79400@6f {
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compatible = "microchip,mcp7940x";
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reg = <0x6f>;
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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ti,pindir-d0-out-d1-in;
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status = "okay";
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display-controller@0 {
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compatible = "orisetech,otm3225a";
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reg = <0>;
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spi-max-frequency = <1000000>;
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// SPI mode 3
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spi-cpol;
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spi-cpha;
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status = "okay";
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};
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};
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/*
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* Disable soc's rtc as we have no VBAT for it. This makes the board
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* rtc (Microchip MCP79400) the default rtc device 'rtc0'.
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*/
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&rtc {
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status = "disabled";
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};
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&lcdc {
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status = "okay";
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};
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&elm {
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status = "okay";
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};
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#include "tps65910.dtsi"
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&tps {
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vcc1-supply = <&vbat>;
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vcc2-supply = <&vbat>;
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vcc3-supply = <&vbat>;
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vcc4-supply = <&vbat>;
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vcc5-supply = <&vbat>;
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vcc6-supply = <&vbat>;
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vcc7-supply = <&vbat>;
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vccio-supply = <&vbat>;
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regulators {
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vrtc_reg: regulator@0 {
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regulator-name = "ldo_vrtc";
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regulator-always-on;
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};
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vio_reg: regulator@1 {
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regulator-name = "buck_vdd_ddr";
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regulator-always-on;
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};
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vdd1_reg: regulator@2 {
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/* VDD_MPU voltage limits */
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regulator-name = "buck_vdd_mpu";
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regulator-min-microvolt = <912500>;
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regulator-max-microvolt = <1312500>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdd2_reg: regulator@3 {
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/* VDD_CORE voltage limits */
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regulator-name = "buck_vdd_core";
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regulator-min-microvolt = <912500>;
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|
regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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|
};
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|
vdd3_reg: regulator@4 {
|
|
regulator-name = "boost_res";
|
|
regulator-always-on;
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|
};
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|
vdig1_reg: regulator@5 {
|
|
regulator-name = "ldo_vdig1";
|
|
regulator-always-on;
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|
};
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|
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|
vdig2_reg: regulator@6 {
|
|
regulator-name = "ldo_vdig2";
|
|
regulator-always-on;
|
|
};
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|
|
|
vpll_reg: regulator@7 {
|
|
regulator-name = "ldo_vpll";
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdac_reg: regulator@8 {
|
|
regulator-name = "ldo_vdac";
|
|
regulator-always-on;
|
|
};
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|
|
|
vaux1_reg: regulator@9 {
|
|
regulator-name = "ldo_vaux1";
|
|
regulator-always-on;
|
|
};
|
|
|
|
vaux2_reg: regulator@10 {
|
|
regulator-name = "ldo_vaux2";
|
|
regulator-always-on;
|
|
};
|
|
|
|
vaux33_reg: regulator@11 {
|
|
regulator-name = "ldo_vaux33";
|
|
regulator-always-on;
|
|
};
|
|
|
|
vmmc_reg: regulator@12 {
|
|
regulator-name = "ldo_vmmc";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vbb_reg: regulator@13 {
|
|
regulator-name = "bat_vbb";
|
|
};
|
|
};
|
|
};
|
|
|
|
&mac {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
dual_emac; /* no switch, two distinct MACs */
|
|
status = "okay";
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
status = "okay";
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
ethphy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy-handle = <ðphy0>;
|
|
phy-mode = "mii";
|
|
dual_emac_res_vlan = <1>;
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy-handle = <ðphy1>;
|
|
phy-mode = "mii";
|
|
dual_emac_res_vlan = <2>;
|
|
};
|
|
|
|
&tscadc {
|
|
status = "okay";
|
|
tsc {
|
|
ti,wires = <4>;
|
|
ti,x-plate-resistance = <200>;
|
|
ti,coordinate-readouts = <5>;
|
|
ti,wire-config = <0x01 0x10 0x22 0x33>;
|
|
ti,charge-delay = <0x400>;
|
|
};
|
|
|
|
adc {
|
|
ti,adc-channels = <4 5 6 7>;
|
|
};
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmc_reg>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
non-removable;
|
|
};
|
|
|
|
&mmc2 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmc_reg>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins>;
|
|
cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
&sham {
|
|
status = "okay";
|
|
};
|
|
|
|
&aes {
|
|
status = "okay";
|
|
};
|
|
|
|
&dcan0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcan0_pins>;
|
|
};
|