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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7e34f4e4aa
In some circumstances the RC6 context can get corrupted. We can detect this and take the required action, that is disable RC6 and runtime PM. The HW recovers from the corrupted state after a system suspend/resume cycle, so detect the recovery and re-enable RC6 and runtime PM. v2: rebase (Mika) v3: - Move intel_suspend_gt_powersave() to the end of the GEM suspend sequence. - Add commit message. v4: - Rebased on intel_uncore_forcewake_put(i915->uncore, ...) API change. v5: rebased on gem/gt split (Mika) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
94 lines
4.0 KiB
C
94 lines
4.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PM_H__
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#define __INTEL_PM_H__
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#include <linux/types.h>
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#include "i915_reg.h"
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struct drm_device;
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struct drm_i915_private;
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struct i915_request;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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struct skl_ddb_allocation;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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void intel_init_clock_gating(struct drm_i915_private *dev_priv);
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void intel_suspend_hw(struct drm_i915_private *dev_priv);
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int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
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void intel_update_watermarks(struct intel_crtc *crtc);
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void intel_init_pm(struct drm_i915_private *dev_priv);
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
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void intel_pm_setup(struct drm_i915_private *dev_priv);
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void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
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void intel_gpu_ips_teardown(void);
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void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
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void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
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void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
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void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
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void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
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bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);
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void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);
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void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);
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void gen6_rps_busy(struct drm_i915_private *dev_priv);
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void gen6_rps_idle(struct drm_i915_private *dev_priv);
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void gen6_rps_boost(struct i915_request *rq);
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void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb_uv);
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
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struct skl_ddb_allocation *ddb /* out */);
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void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
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struct skl_pipe_wm *out);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct intel_atomic_state *state);
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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const struct skl_wm_level *l2);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool ilk_disable_lp_wm(struct drm_device *dev);
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int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *cstate);
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void intel_init_ipc(struct drm_i915_private *dev_priv);
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void intel_enable_ipc(struct drm_i915_private *dev_priv);
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int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
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int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
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u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
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u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
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u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
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unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
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unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
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unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
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void i915_update_gfx_val(struct drm_i915_private *dev_priv);
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bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
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int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
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void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive);
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bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
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#endif /* __INTEL_PM_H__ */
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