mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 18:25:51 +07:00
2c86e55d2a
Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
599 lines
16 KiB
C
599 lines
16 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/slab.h> /* fault-inject.h is not standalone! */
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#include <linux/fault-inject.h>
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#include "i915_trace.h"
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#include "intel_gt.h"
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#include "intel_gtt.h"
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void stash_init(struct pagestash *stash)
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{
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pagevec_init(&stash->pvec);
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spin_lock_init(&stash->lock);
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}
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static struct page *stash_pop_page(struct pagestash *stash)
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{
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struct page *page = NULL;
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spin_lock(&stash->lock);
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if (likely(stash->pvec.nr))
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page = stash->pvec.pages[--stash->pvec.nr];
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spin_unlock(&stash->lock);
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return page;
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}
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static void stash_push_pagevec(struct pagestash *stash, struct pagevec *pvec)
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{
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unsigned int nr;
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spin_lock_nested(&stash->lock, SINGLE_DEPTH_NESTING);
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nr = min_t(typeof(nr), pvec->nr, pagevec_space(&stash->pvec));
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memcpy(stash->pvec.pages + stash->pvec.nr,
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pvec->pages + pvec->nr - nr,
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sizeof(pvec->pages[0]) * nr);
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stash->pvec.nr += nr;
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spin_unlock(&stash->lock);
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pvec->nr -= nr;
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}
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static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
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{
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struct pagevec stack;
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struct page *page;
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if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
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i915_gem_shrink_all(vm->i915);
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page = stash_pop_page(&vm->free_pages);
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if (page)
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return page;
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if (!vm->pt_kmap_wc)
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return alloc_page(gfp);
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/* Look in our global stash of WC pages... */
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page = stash_pop_page(&vm->i915->mm.wc_stash);
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if (page)
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return page;
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/*
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* Otherwise batch allocate pages to amortize cost of set_pages_wc.
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*
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* We have to be careful as page allocation may trigger the shrinker
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* (via direct reclaim) which will fill up the WC stash underneath us.
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* So we add our WB pages into a temporary pvec on the stack and merge
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* them into the WC stash after all the allocations are complete.
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*/
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pagevec_init(&stack);
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do {
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struct page *page;
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page = alloc_page(gfp);
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if (unlikely(!page))
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break;
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stack.pages[stack.nr++] = page;
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} while (pagevec_space(&stack));
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if (stack.nr && !set_pages_array_wc(stack.pages, stack.nr)) {
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page = stack.pages[--stack.nr];
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/* Merge spare WC pages to the global stash */
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if (stack.nr)
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stash_push_pagevec(&vm->i915->mm.wc_stash, &stack);
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/* Push any surplus WC pages onto the local VM stash */
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if (stack.nr)
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stash_push_pagevec(&vm->free_pages, &stack);
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}
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/* Return unwanted leftovers */
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if (unlikely(stack.nr)) {
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WARN_ON_ONCE(set_pages_array_wb(stack.pages, stack.nr));
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__pagevec_release(&stack);
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}
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return page;
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}
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static void vm_free_pages_release(struct i915_address_space *vm,
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bool immediate)
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{
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struct pagevec *pvec = &vm->free_pages.pvec;
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struct pagevec stack;
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lockdep_assert_held(&vm->free_pages.lock);
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GEM_BUG_ON(!pagevec_count(pvec));
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if (vm->pt_kmap_wc) {
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/*
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* When we use WC, first fill up the global stash and then
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* only if full immediately free the overflow.
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*/
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stash_push_pagevec(&vm->i915->mm.wc_stash, pvec);
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/*
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* As we have made some room in the VM's free_pages,
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* we can wait for it to fill again. Unless we are
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* inside i915_address_space_fini() and must
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* immediately release the pages!
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*/
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if (pvec->nr <= (immediate ? 0 : PAGEVEC_SIZE - 1))
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return;
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/*
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* We have to drop the lock to allow ourselves to sleep,
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* so take a copy of the pvec and clear the stash for
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* others to use it as we sleep.
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*/
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stack = *pvec;
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pagevec_reinit(pvec);
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spin_unlock(&vm->free_pages.lock);
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pvec = &stack;
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set_pages_array_wb(pvec->pages, pvec->nr);
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spin_lock(&vm->free_pages.lock);
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}
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__pagevec_release(pvec);
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}
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static void vm_free_page(struct i915_address_space *vm, struct page *page)
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{
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/*
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* On !llc, we need to change the pages back to WB. We only do so
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* in bulk, so we rarely need to change the page attributes here,
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* but doing so requires a stop_machine() from deep inside arch/x86/mm.
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* To make detection of the possible sleep more likely, use an
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* unconditional might_sleep() for everybody.
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*/
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might_sleep();
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spin_lock(&vm->free_pages.lock);
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while (!pagevec_space(&vm->free_pages.pvec))
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vm_free_pages_release(vm, false);
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GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec) >= PAGEVEC_SIZE);
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pagevec_add(&vm->free_pages.pvec, page);
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spin_unlock(&vm->free_pages.lock);
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}
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void __i915_vm_close(struct i915_address_space *vm)
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{
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struct i915_vma *vma, *vn;
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mutex_lock(&vm->mutex);
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list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
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struct drm_i915_gem_object *obj = vma->obj;
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/* Keep the obj (and hence the vma) alive as _we_ destroy it */
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if (!kref_get_unless_zero(&obj->base.refcount))
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continue;
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atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
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WARN_ON(__i915_vma_unbind(vma));
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__i915_vma_put(vma);
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i915_gem_object_put(obj);
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}
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GEM_BUG_ON(!list_empty(&vm->bound_list));
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mutex_unlock(&vm->mutex);
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}
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void i915_address_space_fini(struct i915_address_space *vm)
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{
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spin_lock(&vm->free_pages.lock);
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if (pagevec_count(&vm->free_pages.pvec))
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vm_free_pages_release(vm, true);
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GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec));
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spin_unlock(&vm->free_pages.lock);
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drm_mm_takedown(&vm->mm);
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mutex_destroy(&vm->mutex);
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}
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static void __i915_vm_release(struct work_struct *work)
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{
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struct i915_address_space *vm =
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container_of(work, struct i915_address_space, rcu.work);
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vm->cleanup(vm);
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i915_address_space_fini(vm);
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kfree(vm);
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}
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void i915_vm_release(struct kref *kref)
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{
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struct i915_address_space *vm =
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container_of(kref, struct i915_address_space, ref);
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GEM_BUG_ON(i915_is_ggtt(vm));
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trace_i915_ppgtt_release(vm);
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queue_rcu_work(vm->i915->wq, &vm->rcu);
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}
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void i915_address_space_init(struct i915_address_space *vm, int subclass)
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{
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kref_init(&vm->ref);
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INIT_RCU_WORK(&vm->rcu, __i915_vm_release);
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atomic_set(&vm->open, 1);
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/*
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* The vm->mutex must be reclaim safe (for use in the shrinker).
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* Do a dummy acquire now under fs_reclaim so that any allocation
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* attempt holding the lock is immediately reported by lockdep.
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*/
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mutex_init(&vm->mutex);
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lockdep_set_subclass(&vm->mutex, subclass);
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i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
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GEM_BUG_ON(!vm->total);
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drm_mm_init(&vm->mm, 0, vm->total);
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vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
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stash_init(&vm->free_pages);
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INIT_LIST_HEAD(&vm->bound_list);
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}
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void clear_pages(struct i915_vma *vma)
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{
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GEM_BUG_ON(!vma->pages);
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if (vma->pages != vma->obj->mm.pages) {
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sg_free_table(vma->pages);
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kfree(vma->pages);
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}
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vma->pages = NULL;
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memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
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}
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static int __setup_page_dma(struct i915_address_space *vm,
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struct i915_page_dma *p,
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gfp_t gfp)
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{
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p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL);
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if (unlikely(!p->page))
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return -ENOMEM;
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p->daddr = dma_map_page_attrs(vm->dma,
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p->page, 0, PAGE_SIZE,
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PCI_DMA_BIDIRECTIONAL,
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DMA_ATTR_SKIP_CPU_SYNC |
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DMA_ATTR_NO_WARN);
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if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
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vm_free_page(vm, p->page);
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return -ENOMEM;
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}
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return 0;
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}
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int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p)
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{
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return __setup_page_dma(vm, p, __GFP_HIGHMEM);
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}
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void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p)
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{
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dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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vm_free_page(vm, p->page);
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}
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void
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fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
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{
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kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
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}
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int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
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{
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unsigned long size;
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/*
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* In order to utilize 64K pages for an object with a size < 2M, we will
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* need to support a 64K scratch page, given that every 16th entry for a
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* page-table operating in 64K mode must point to a properly aligned 64K
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* region, including any PTEs which happen to point to scratch.
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*
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* This is only relevant for the 48b PPGTT where we support
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* huge-gtt-pages, see also i915_vma_insert(). However, as we share the
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* scratch (read-only) between all vm, we create one 64k scratch page
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* for all.
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*/
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size = I915_GTT_PAGE_SIZE_4K;
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if (i915_vm_is_4lvl(vm) &&
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HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
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size = I915_GTT_PAGE_SIZE_64K;
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gfp |= __GFP_NOWARN;
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}
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gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL;
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do {
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unsigned int order = get_order(size);
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struct page *page;
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dma_addr_t addr;
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page = alloc_pages(gfp, order);
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if (unlikely(!page))
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goto skip;
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addr = dma_map_page_attrs(vm->dma,
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page, 0, size,
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PCI_DMA_BIDIRECTIONAL,
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DMA_ATTR_SKIP_CPU_SYNC |
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DMA_ATTR_NO_WARN);
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if (unlikely(dma_mapping_error(vm->dma, addr)))
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goto free_page;
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if (unlikely(!IS_ALIGNED(addr, size)))
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goto unmap_page;
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vm->scratch[0].base.page = page;
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vm->scratch[0].base.daddr = addr;
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vm->scratch_order = order;
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return 0;
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unmap_page:
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dma_unmap_page(vm->dma, addr, size, PCI_DMA_BIDIRECTIONAL);
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free_page:
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__free_pages(page, order);
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skip:
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if (size == I915_GTT_PAGE_SIZE_4K)
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return -ENOMEM;
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size = I915_GTT_PAGE_SIZE_4K;
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gfp &= ~__GFP_NOWARN;
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} while (1);
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}
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void cleanup_scratch_page(struct i915_address_space *vm)
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{
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struct i915_page_dma *p = px_base(&vm->scratch[0]);
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unsigned int order = vm->scratch_order;
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dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT,
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PCI_DMA_BIDIRECTIONAL);
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__free_pages(p->page, order);
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}
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void free_scratch(struct i915_address_space *vm)
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{
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int i;
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if (!px_dma(&vm->scratch[0])) /* set to 0 on clones */
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return;
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for (i = 1; i <= vm->top; i++) {
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if (!px_dma(&vm->scratch[i]))
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break;
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cleanup_page_dma(vm, px_base(&vm->scratch[i]));
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}
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cleanup_scratch_page(vm);
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}
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void gtt_write_workarounds(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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/*
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* This function is for gtt related workarounds. This function is
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* called on driver load and after a GPU reset, so you can place
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* workarounds here even if they get overwritten by GPU reset.
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*/
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/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
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if (IS_BROADWELL(i915))
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intel_uncore_write(uncore,
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GEN8_L3_LRA_1_GPGPU,
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GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
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else if (IS_CHERRYVIEW(i915))
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intel_uncore_write(uncore,
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GEN8_L3_LRA_1_GPGPU,
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GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
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else if (IS_GEN9_LP(i915))
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intel_uncore_write(uncore,
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GEN8_L3_LRA_1_GPGPU,
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GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
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else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
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intel_uncore_write(uncore,
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GEN8_L3_LRA_1_GPGPU,
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GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
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/*
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* To support 64K PTEs we need to first enable the use of the
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* Intermediate-Page-Size(IPS) bit of the PDE field via some magical
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* mmio, otherwise the page-walker will simply ignore the IPS bit. This
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* shouldn't be needed after GEN10.
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*
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* 64K pages were first introduced from BDW+, although technically they
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* only *work* from gen9+. For pre-BDW we instead have the option for
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* 32K pages, but we don't currently have any support for it in our
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* driver.
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*/
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if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
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INTEL_GEN(i915) <= 10)
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intel_uncore_rmw(uncore,
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GEN8_GAMW_ECO_DEV_RW_IA,
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0,
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GAMW_ECO_ENABLE_64K_IPS_FIELD);
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if (IS_GEN_RANGE(i915, 8, 11)) {
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bool can_use_gtt_cache = true;
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/*
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* According to the BSpec if we use 2M/1G pages then we also
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* need to disable the GTT cache. At least on BDW we can see
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* visual corruption when using 2M pages, and not disabling the
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* GTT cache.
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*/
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if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M))
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can_use_gtt_cache = false;
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/* WaGttCachingOffByDefault */
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intel_uncore_write(uncore,
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HSW_GTT_CACHE_EN,
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can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
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WARN_ON_ONCE(can_use_gtt_cache &&
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intel_uncore_read(uncore,
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HSW_GTT_CACHE_EN) == 0);
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}
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}
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u64 gen8_pte_encode(dma_addr_t addr,
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enum i915_cache_level level,
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u32 flags)
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{
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gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
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if (unlikely(flags & PTE_READ_ONLY))
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pte &= ~_PAGE_RW;
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switch (level) {
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case I915_CACHE_NONE:
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pte |= PPAT_UNCACHED;
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break;
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case I915_CACHE_WT:
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pte |= PPAT_DISPLAY_ELLC;
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break;
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default:
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pte |= PPAT_CACHED;
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break;
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}
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return pte;
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}
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static void tgl_setup_private_ppat(struct intel_uncore *uncore)
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{
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/* TGL doesn't support LLC or AGE settings */
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intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
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intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
|
|
intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
|
|
}
|
|
|
|
static void cnl_setup_private_ppat(struct intel_uncore *uncore)
|
|
{
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(0),
|
|
GEN8_PPAT_WB | GEN8_PPAT_LLC);
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(1),
|
|
GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(2),
|
|
GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(3),
|
|
GEN8_PPAT_UC);
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(4),
|
|
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(5),
|
|
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(6),
|
|
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
|
|
intel_uncore_write(uncore,
|
|
GEN10_PAT_INDEX(7),
|
|
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
|
|
}
|
|
|
|
/*
|
|
* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
|
|
* bits. When using advanced contexts each context stores its own PAT, but
|
|
* writing this data shouldn't be harmful even in those cases.
|
|
*/
|
|
static void bdw_setup_private_ppat(struct intel_uncore *uncore)
|
|
{
|
|
u64 pat;
|
|
|
|
pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
|
|
GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
|
|
GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
|
|
GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
|
|
GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
|
|
GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
|
|
GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
|
|
GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
|
|
|
|
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
|
|
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
|
|
}
|
|
|
|
static void chv_setup_private_ppat(struct intel_uncore *uncore)
|
|
{
|
|
u64 pat;
|
|
|
|
/*
|
|
* Map WB on BDW to snooped on CHV.
|
|
*
|
|
* Only the snoop bit has meaning for CHV, the rest is
|
|
* ignored.
|
|
*
|
|
* The hardware will never snoop for certain types of accesses:
|
|
* - CPU GTT (GMADR->GGTT->no snoop->memory)
|
|
* - PPGTT page tables
|
|
* - some other special cycles
|
|
*
|
|
* As with BDW, we also need to consider the following for GT accesses:
|
|
* "For GGTT, there is NO pat_sel[2:0] from the entry,
|
|
* so RTL will always use the value corresponding to
|
|
* pat_sel = 000".
|
|
* Which means we must set the snoop bit in PAT entry 0
|
|
* in order to keep the global status page working.
|
|
*/
|
|
|
|
pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
|
|
GEN8_PPAT(1, 0) |
|
|
GEN8_PPAT(2, 0) |
|
|
GEN8_PPAT(3, 0) |
|
|
GEN8_PPAT(4, CHV_PPAT_SNOOP) |
|
|
GEN8_PPAT(5, CHV_PPAT_SNOOP) |
|
|
GEN8_PPAT(6, CHV_PPAT_SNOOP) |
|
|
GEN8_PPAT(7, CHV_PPAT_SNOOP);
|
|
|
|
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
|
|
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
|
|
}
|
|
|
|
void setup_private_pat(struct intel_uncore *uncore)
|
|
{
|
|
struct drm_i915_private *i915 = uncore->i915;
|
|
|
|
GEM_BUG_ON(INTEL_GEN(i915) < 8);
|
|
|
|
if (INTEL_GEN(i915) >= 12)
|
|
tgl_setup_private_ppat(uncore);
|
|
else if (INTEL_GEN(i915) >= 10)
|
|
cnl_setup_private_ppat(uncore);
|
|
else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
|
|
chv_setup_private_ppat(uncore);
|
|
else
|
|
bdw_setup_private_ppat(uncore);
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
#include "selftests/mock_gtt.c"
|
|
#endif
|