mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 00:46:55 +07:00
f57091767a
Pull x86 cache quality monitoring update from Thomas Gleixner: "This update provides a complete rewrite of the Cache Quality Monitoring (CQM) facility. The existing CQM support was duct taped into perf with a lot of issues and the attempts to fix those turned out to be incomplete and horrible. After lengthy discussions it was decided to integrate the CQM support into the Resource Director Technology (RDT) facility, which is the obvious choise as in hardware CQM is part of RDT. This allowed to add Memory Bandwidth Monitoring support on top. As a result the mechanisms for allocating cache/memory bandwidth and the corresponding monitoring mechanisms are integrated into a single management facility with a consistent user interface" * 'x86-cache-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits) x86/intel_rdt: Turn off most RDT features on Skylake x86/intel_rdt: Add command line options for resource director technology x86/intel_rdt: Move special case code for Haswell to a quirk function x86/intel_rdt: Remove redundant ternary operator on return x86/intel_rdt/cqm: Improve limbo list processing x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug x86/intel_rdt: Modify the intel_pqr_state for better performance x86/intel_rdt/cqm: Clear the default RMID during hotcpu x86/intel_rdt: Show bitmask of shareable resource with other executing units x86/intel_rdt/mbm: Handle counter overflow x86/intel_rdt/mbm: Add mbm counter initialization x86/intel_rdt/mbm: Basic counting of MBM events (total and local) x86/intel_rdt/cqm: Add CPU hotplug support x86/intel_rdt/cqm: Add sched_in support x86/intel_rdt: Introduce rdt_enable_key for scheduling x86/intel_rdt/cqm: Add mount,umount support x86/intel_rdt/cqm: Add rmdir support x86/intel_rdt: Separate the ctrl bits from rmdir x86/intel_rdt/cqm: Add mon_data x86/intel_rdt: Prepare for RDT monitor data support ...
314 lines
8.5 KiB
C
314 lines
8.5 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* This file handles the architecture-dependent parts of process handling..
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*/
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#include <linux/cpu.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/elfcore.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/user.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <linux/mc146818rtc.h>
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#include <linux/export.h>
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#include <linux/kallsyms.h>
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#include <linux/ptrace.h>
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#include <linux/personality.h>
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#include <linux/percpu.h>
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#include <linux/prctl.h>
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#include <linux/ftrace.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/kdebug.h>
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#include <linux/syscalls.h>
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#include <asm/pgtable.h>
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#include <asm/ldt.h>
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#include <asm/processor.h>
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#include <asm/fpu/internal.h>
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#include <asm/desc.h>
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#ifdef CONFIG_MATH_EMULATION
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#include <asm/math_emu.h>
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#endif
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#include <linux/err.h>
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#include <asm/tlbflush.h>
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#include <asm/cpu.h>
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#include <asm/syscalls.h>
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#include <asm/debugreg.h>
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#include <asm/switch_to.h>
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#include <asm/vm86.h>
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#include <asm/intel_rdt_sched.h>
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#include <asm/proto.h>
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void __show_regs(struct pt_regs *regs, int all)
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{
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unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
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unsigned long d0, d1, d2, d3, d6, d7;
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unsigned long sp;
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unsigned short ss, gs;
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if (user_mode(regs)) {
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sp = regs->sp;
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ss = regs->ss;
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gs = get_user_gs(regs);
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} else {
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sp = kernel_stack_pointer(regs);
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savesegment(ss, ss);
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savesegment(gs, gs);
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}
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printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
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printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
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raw_smp_processor_id());
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printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
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regs->ax, regs->bx, regs->cx, regs->dx);
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printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
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regs->si, regs->di, regs->bp, sp);
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printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
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(u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
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if (!all)
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return;
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cr0 = read_cr0();
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cr2 = read_cr2();
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cr3 = __read_cr3();
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cr4 = __read_cr4();
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printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
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cr0, cr2, cr3, cr4);
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get_debugreg(d0, 0);
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get_debugreg(d1, 1);
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get_debugreg(d2, 2);
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get_debugreg(d3, 3);
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get_debugreg(d6, 6);
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get_debugreg(d7, 7);
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/* Only print out debug registers if they are in their non-default state. */
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if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
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(d6 == DR6_RESERVED) && (d7 == 0x400))
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return;
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printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
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d0, d1, d2, d3);
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printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
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d6, d7);
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}
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void release_thread(struct task_struct *dead_task)
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{
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BUG_ON(dead_task->mm);
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release_vm86_irqs(dead_task);
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}
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int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
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unsigned long arg, struct task_struct *p, unsigned long tls)
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{
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struct pt_regs *childregs = task_pt_regs(p);
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struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
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struct inactive_task_frame *frame = &fork_frame->frame;
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struct task_struct *tsk;
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int err;
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frame->bp = 0;
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frame->ret_addr = (unsigned long) ret_from_fork;
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p->thread.sp = (unsigned long) fork_frame;
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p->thread.sp0 = (unsigned long) (childregs+1);
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memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
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if (unlikely(p->flags & PF_KTHREAD)) {
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/* kernel thread */
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memset(childregs, 0, sizeof(struct pt_regs));
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frame->bx = sp; /* function */
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frame->di = arg;
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p->thread.io_bitmap_ptr = NULL;
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return 0;
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}
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frame->bx = 0;
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*childregs = *current_pt_regs();
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childregs->ax = 0;
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if (sp)
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childregs->sp = sp;
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task_user_gs(p) = get_user_gs(current_pt_regs());
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p->thread.io_bitmap_ptr = NULL;
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tsk = current;
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err = -ENOMEM;
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if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
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p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
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IO_BITMAP_BYTES, GFP_KERNEL);
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if (!p->thread.io_bitmap_ptr) {
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p->thread.io_bitmap_max = 0;
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return -ENOMEM;
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}
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set_tsk_thread_flag(p, TIF_IO_BITMAP);
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}
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err = 0;
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/*
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* Set a new TLS for the child thread?
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*/
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if (clone_flags & CLONE_SETTLS)
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err = do_set_thread_area(p, -1,
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(struct user_desc __user *)tls, 0);
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if (err && p->thread.io_bitmap_ptr) {
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kfree(p->thread.io_bitmap_ptr);
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p->thread.io_bitmap_max = 0;
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}
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return err;
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}
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void
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start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
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{
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set_user_gs(regs, 0);
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regs->fs = 0;
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regs->ds = __USER_DS;
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regs->es = __USER_DS;
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regs->ss = __USER_DS;
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regs->cs = __USER_CS;
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regs->ip = new_ip;
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regs->sp = new_sp;
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regs->flags = X86_EFLAGS_IF;
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force_iret();
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}
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EXPORT_SYMBOL_GPL(start_thread);
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/*
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* switch_to(x,y) should switch tasks from x to y.
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*
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* We fsave/fwait so that an exception goes off at the right time
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* (as a call from the fsave or fwait in effect) rather than to
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* the wrong process. Lazy FP saving no longer makes any sense
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* with modern CPU's, and this simplifies a lot of things (SMP
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* and UP become the same).
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*
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* NOTE! We used to use the x86 hardware context switching. The
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* reason for not using it any more becomes apparent when you
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* try to recover gracefully from saved state that is no longer
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* valid (stale segment register values in particular). With the
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* hardware task-switch, there is no way to fix up bad state in
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* a reasonable manner.
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*
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* The fact that Intel documents the hardware task-switching to
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* be slow is a fairly red herring - this code is not noticeably
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* faster. However, there _is_ some room for improvement here,
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* so the performance issues may eventually be a valid point.
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* More important, however, is the fact that this allows us much
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* more flexibility.
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*
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* The return value (in %ax) will be the "prev" task after
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* the task-switch, and shows up in ret_from_fork in entry.S,
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* for example.
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*/
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__visible __notrace_funcgraph struct task_struct *
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__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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{
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struct thread_struct *prev = &prev_p->thread,
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*next = &next_p->thread;
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struct fpu *prev_fpu = &prev->fpu;
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struct fpu *next_fpu = &next->fpu;
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int cpu = smp_processor_id();
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struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
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/* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
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switch_fpu_prepare(prev_fpu, cpu);
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/*
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* Save away %gs. No need to save %fs, as it was saved on the
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* stack on entry. No need to save %es and %ds, as those are
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* always kernel segments while inside the kernel. Doing this
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* before setting the new TLS descriptors avoids the situation
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* where we temporarily have non-reloadable segments in %fs
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* and %gs. This could be an issue if the NMI handler ever
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* used %fs or %gs (it does not today), or if the kernel is
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* running inside of a hypervisor layer.
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*/
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lazy_save_gs(prev->gs);
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/*
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* Load the per-thread Thread-Local Storage descriptor.
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*/
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load_TLS(next, cpu);
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/*
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* Restore IOPL if needed. In normal use, the flags restore
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* in the switch assembly will handle this. But if the kernel
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* is running virtualized at a non-zero CPL, the popf will
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* not restore flags, so it must be done in a separate step.
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*/
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if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
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set_iopl_mask(next->iopl);
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/*
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* Now maybe handle debug registers and/or IO bitmaps
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*/
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if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV ||
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task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
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__switch_to_xtra(prev_p, next_p, tss);
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/*
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* Leave lazy mode, flushing any hypercalls made here.
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* This must be done before restoring TLS segments so
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* the GDT and LDT are properly updated, and must be
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* done before fpu__restore(), so the TS bit is up
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* to date.
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*/
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arch_end_context_switch(next_p);
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/*
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* Reload esp0 and cpu_current_top_of_stack. This changes
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* current_thread_info().
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*/
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load_sp0(tss, next);
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this_cpu_write(cpu_current_top_of_stack,
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(unsigned long)task_stack_page(next_p) +
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THREAD_SIZE);
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/*
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* Restore %gs if needed (which is common)
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*/
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if (prev->gs | next->gs)
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lazy_load_gs(next->gs);
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switch_fpu_finish(next_fpu, cpu);
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this_cpu_write(current_task, next_p);
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/* Load the Intel cache allocation PQR MSR. */
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intel_rdt_sched_in();
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return prev_p;
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}
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SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
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{
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return do_arch_prctl_common(current, option, arg2);
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}
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