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e1f1ae8002
The module reset code in the Renesas CPG/MSSR driver uses
read-modify-write (RMW) operations to write to a Software Reset Register
(SRCRn), and simple writes to write to a Software Reset Clearing
Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
User's Manuals.
However, this may cause a race condition when two devices are reset in
parallel: if the reset for device A completes in the middle of the RMW
operation for device B, device A may be reset again, causing subtle
failures (e.g. i2c timeouts):
thread A thread B
-------- --------
val = SRCRn
val |= bit A
SRCRn = val
delay
val = SRCRn (bit A is set)
SRSTCLRn = bit A
(bit A in SRCRn is cleared)
val |= bit B
SRCRn = val (bit A and B are set)
This can be reproduced on e.g. Salvator-XS using:
$ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
$ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &
i2c-rcar e6510000.i2c: error -110 : 40000002
i2c-rcar e66d8000.i2c: error -110 : 40000002
According to the R-Car Gen3 Hardware Manual Errata for Rev.
0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
User's Manual, writes to SRCRn do not require read-modify-write cycles.
Note that the R-Car Gen2 Hardware User's Manual has not been updated
yet, and still says a read-modify-write sequence is required. According
to the hardware team, the reset hardware block is the same on both R-Car
Gen2 and Gen3, though.
Hence fix the issue by replacing the read-modify-write operations on
SRCRn by simple writes.
Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com>
Fixes:
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.. | ||
actions | ||
analogbits | ||
at91 | ||
axis | ||
axs10x | ||
bcm | ||
berlin | ||
davinci | ||
h8300 | ||
hisilicon | ||
imgtec | ||
imx | ||
ingenic | ||
keystone | ||
loongson1 | ||
mediatek | ||
meson | ||
microchip | ||
mmp | ||
mvebu | ||
mxs | ||
nxp | ||
pistachio | ||
pxa | ||
qcom | ||
renesas | ||
rockchip | ||
samsung | ||
sifive | ||
sirf | ||
socfpga | ||
spear | ||
sprd | ||
st | ||
sunxi | ||
sunxi-ng | ||
tegra | ||
ti | ||
uniphier | ||
ux500 | ||
versatile | ||
x86 | ||
zte | ||
zynq | ||
zynqmp | ||
clk-asm9260.c | ||
clk-aspeed.c | ||
clk-axi-clkgen.c | ||
clk-axm5516.c | ||
clk-bd718x7.c | ||
clk-bulk.c | ||
clk-cdce706.c | ||
clk-cdce925.c | ||
clk-clps711x.c | ||
clk-composite.c | ||
clk-conf.c | ||
clk-cs2000-cp.c | ||
clk-devres.c | ||
clk-divider.c | ||
clk-efm32gg.c | ||
clk-fixed-factor.c | ||
clk-fixed-mmio.c | ||
clk-fixed-rate.c | ||
clk-fractional-divider.c | ||
clk-gate.c | ||
clk-gemini.c | ||
clk-gpio.c | ||
clk-hi655x.c | ||
clk-highbank.c | ||
clk-hsdk-pll.c | ||
clk-lochnagar.c | ||
clk-max9485.c | ||
clk-max77686.c | ||
clk-milbeaut.c | ||
clk-moxart.c | ||
clk-multiplier.c | ||
clk-mux.c | ||
clk-nomadik.c | ||
clk-npcm7xx.c | ||
clk-nspire.c | ||
clk-oxnas.c | ||
clk-palmas.c | ||
clk-pwm.c | ||
clk-qoriq.c | ||
clk-rk808.c | ||
clk-s2mps11.c | ||
clk-scmi.c | ||
clk-scpi.c | ||
clk-si514.c | ||
clk-si544.c | ||
clk-si570.c | ||
clk-si5341.c | ||
clk-si5351.c | ||
clk-si5351.h | ||
clk-stm32f4.c | ||
clk-stm32h7.c | ||
clk-stm32mp1.c | ||
clk-tango4.c | ||
clk-twl6040.c | ||
clk-u300.c | ||
clk-versaclock5.c | ||
clk-vt8500.c | ||
clk-wm831x.c | ||
clk-xgene.c | ||
clk.c | ||
clk.h | ||
clkdev.c | ||
Kconfig | ||
Makefile |