Bjorn Helgaas c00054f540 PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD ... Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream) device using the capability pointer of the *child* (downstream) device, which corrupted some random word of the parent's config space. Use the parent's L1 SS capability pointer to program its LTR_L1.2_THRESHOLD. Fixes: aeda9adeba ("PCI/ASPM: Configure L1 substate settings") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com> CC: stable@vger.kernel.org # v4.11+ CC: Rajat Jain <rajatja@google.com>		2017-11-14 08:32:32 -06:00
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aer	Merge branch 'pci/trivial' into next	2017-09-07 13:24:20 -05:00
aspm.c	PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD	2017-11-14 08:32:32 -06:00
Kconfig	PCI/ASPM: Add support for L1 substates	2017-02-14 17:43:51 -06:00
Makefile	PCI: Add Precision Time Measurement (PTM) support	2016-08-15 13:44:08 -05:00
pcie-dpc.c	PCI/DPC: Add local struct device pointers	2017-08-24 11:30:02 -05:00
pme.c	PCI / PM: Fix native PME handling during system suspend/resume	2017-07-13 01:50:07 +02:00
portdrv_acpi.c	Merge branches 'pci/dpc', 'pci/resource' and 'pci/thunderbolt' into next	2016-05-03 11:49:21 -05:00
portdrv_bus.c	PCI: Fix whitespace, capitalization, and spelling errors	2013-11-14 11:28:18 -07:00
portdrv_core.c	PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment	2017-06-16 19:19:28 -05:00
portdrv_pci.c	dmi: Mark all struct dmi_system_id instances const	2017-09-14 11:59:30 +02:00
portdrv.h	PCI/portdrv: Support multiple interrupts for MSI as well as MSI-X	2017-06-16 18:04:13 -05:00
ptm.c	PCI: Add PTM clock granularity information	2016-08-25 08:32:34 -05:00