mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 12:32:00 +07:00
b8ab62ff71
According to arm cpus binding doc,
"
On 32-bit ARM v7 or later systems this property is
required and matches the CPU MPIDR[23:0] register
bits.
Bits [23:0] in the reg cell must be set to
bits [23:0] in MPIDR.
All other bits in the reg cell must be set to 0.
"
In i.MX7ULP, the MPIDR[23:0] is 0xf00, not 0, so fix it.
Otherwise there will be warning:
"DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map"
Fixes: 20434dc92c ("ARM: dts: imx: add common imx7ulp dtsi support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
462 lines
12 KiB
Plaintext
462 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
|
* Copyright 2017-2018 NXP
|
|
* Dong Aisheng <aisheng.dong@nxp.com>
|
|
*/
|
|
|
|
#include <dt-bindings/clock/imx7ulp-clock.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
#include "imx7ulp-pinfunc.h"
|
|
|
|
/ {
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
gpio0 = &gpio_ptc;
|
|
gpio1 = &gpio_ptd;
|
|
gpio2 = &gpio_pte;
|
|
gpio3 = &gpio_ptf;
|
|
i2c0 = &lpi2c6;
|
|
i2c1 = &lpi2c7;
|
|
mmc0 = &usdhc0;
|
|
mmc1 = &usdhc1;
|
|
serial0 = &lpuart4;
|
|
serial1 = &lpuart5;
|
|
serial2 = &lpuart6;
|
|
serial3 = &lpuart7;
|
|
usbphy0 = &usbphy1;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@f00 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <0xf00>;
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@40021000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x40021000 0x1000>,
|
|
<0x40022000 0x1000>;
|
|
};
|
|
|
|
rosc: clock-rosc {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "rosc";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sosc: clock-sosc {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "sosc";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sirc: clock-sirc {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <16000000>;
|
|
clock-output-names = "sirc";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
firc: clock-firc {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <48000000>;
|
|
clock-output-names = "firc";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
upll: clock-upll {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <480000000>;
|
|
clock-output-names = "upll";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ahbbridge0: bus@40000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40000000 0x800000>;
|
|
ranges;
|
|
|
|
edma1: dma-controller@40080000 {
|
|
#dma-cells = <2>;
|
|
compatible = "fsl,imx7ulp-edma";
|
|
reg = <0x40080000 0x2000>,
|
|
<0x40210000 0x1000>;
|
|
dma-channels = <32>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "dma", "dmamux0";
|
|
clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
|
|
<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
|
|
};
|
|
|
|
crypto: crypto@40240000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40240000 0x10000>;
|
|
ranges = <0 0x40240000 0x10000>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
|
|
<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
|
|
clock-names = "aclk", "ipg";
|
|
|
|
sec_jr0: jr0@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr1@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
lpuart4: serial@402d0000 {
|
|
compatible = "fsl,imx7ulp-lpuart";
|
|
reg = <0x402d0000 0x1000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
|
assigned-clock-rates = <24000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@402e0000 {
|
|
compatible = "fsl,imx7ulp-lpuart";
|
|
reg = <0x402e0000 0x1000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm4: pwm@40250000 {
|
|
compatible = "fsl,imx7ulp-pwm";
|
|
reg = <0x40250000 0x1000>;
|
|
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm5: tpm@40260000 {
|
|
compatible = "fsl,imx7ulp-tpm";
|
|
reg = <0x40260000 0x1000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
|
<&pcc2 IMX7ULP_CLK_LPTPM5>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
usbotg1: usb@40330000 {
|
|
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
|
|
reg = <0x40330000 0x200>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_USB0>;
|
|
phys = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc1 0>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x8>;
|
|
rx-burst-size-dword = <0x8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc1: usbmisc@40330200 {
|
|
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
|
|
#index-cells = <1>;
|
|
reg = <0x40330200 0x200>;
|
|
};
|
|
|
|
usbphy1: usb-phy@40350000 {
|
|
compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
|
|
reg = <0x40350000 0x1000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usdhc0: mmc@40370000 {
|
|
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x40370000 0x10000>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
|
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
|
<&pcc2 IMX7ULP_CLK_USDHC0>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: mmc@40380000 {
|
|
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x40380000 0x10000>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
|
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
|
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scg1: clock-controller@403e0000 {
|
|
compatible = "fsl,imx7ulp-scg1";
|
|
reg = <0x403e0000 0x10000>;
|
|
clocks = <&rosc>, <&sosc>, <&sirc>,
|
|
<&firc>, <&upll>;
|
|
clock-names = "rosc", "sosc", "sirc",
|
|
"firc", "upll";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
wdog1: watchdog@403d0000 {
|
|
compatible = "fsl,imx7ulp-wdt";
|
|
reg = <0x403d0000 0x10000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
|
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
|
assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
|
|
timeout-sec = <40>;
|
|
};
|
|
|
|
pcc2: clock-controller@403f0000 {
|
|
compatible = "fsl,imx7ulp-pcc2";
|
|
reg = <0x403f0000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
|
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
|
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
|
<&scg1 IMX7ULP_CLK_UPLL>,
|
|
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
|
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
|
<&scg1 IMX7ULP_CLK_ROSC>,
|
|
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
|
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
|
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
|
"upll", "sosc_bus_clk",
|
|
"firc_bus_clk", "rosc", "spll_bus_clk";
|
|
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
|
};
|
|
|
|
smc1: clock-controller@40410000 {
|
|
compatible = "fsl,imx7ulp-smc1";
|
|
reg = <0x40410000 0x1000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
|
|
<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
|
|
clock-names = "divcore", "hsrun_divcore";
|
|
};
|
|
|
|
pcc3: clock-controller@40b30000 {
|
|
compatible = "fsl,imx7ulp-pcc3";
|
|
reg = <0x40b30000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
|
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
|
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
|
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
|
<&scg1 IMX7ULP_CLK_UPLL>,
|
|
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
|
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
|
<&scg1 IMX7ULP_CLK_ROSC>,
|
|
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
|
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
|
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
|
"upll", "sosc_bus_clk",
|
|
"firc_bus_clk", "rosc", "spll_bus_clk";
|
|
};
|
|
};
|
|
|
|
ahbbridge1: bus@40800000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40800000 0x800000>;
|
|
ranges;
|
|
|
|
lpi2c6: i2c@40a40000 {
|
|
compatible = "fsl,imx7ulp-lpi2c";
|
|
reg = <0x40a40000 0x10000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c7: i2c@40a50000 {
|
|
compatible = "fsl,imx7ulp-lpi2c";
|
|
reg = <0x40a50000 0x10000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart6: serial@40a60000 {
|
|
compatible = "fsl,imx7ulp-lpuart";
|
|
reg = <0x40a60000 0x1000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart7: serial@40a70000 {
|
|
compatible = "fsl,imx7ulp-lpuart";
|
|
reg = <0x40a70000 0x1000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
|
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
memory-controller@40ab0000 {
|
|
compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
|
|
reg = <0x40ab0000 0x1000>;
|
|
clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
|
|
};
|
|
|
|
iomuxc1: pinctrl@40ac0000 {
|
|
compatible = "fsl,imx7ulp-iomuxc1";
|
|
reg = <0x40ac0000 0x1000>;
|
|
};
|
|
|
|
gpio_ptc: gpio@40ae0000 {
|
|
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
|
reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
|
<&pcc3 IMX7ULP_CLK_PCTLC>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 0 32>;
|
|
};
|
|
|
|
gpio_ptd: gpio@40af0000 {
|
|
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
|
reg = <0x40af0000 0x1000 0x400f0040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
|
<&pcc3 IMX7ULP_CLK_PCTLD>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 32 32>;
|
|
};
|
|
|
|
gpio_pte: gpio@40b00000 {
|
|
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
|
reg = <0x40b00000 0x1000 0x400f0080 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
|
<&pcc3 IMX7ULP_CLK_PCTLE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 64 32>;
|
|
};
|
|
|
|
gpio_ptf: gpio@40b10000 {
|
|
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
|
reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
|
<&pcc3 IMX7ULP_CLK_PCTLF>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 96 32>;
|
|
};
|
|
};
|
|
|
|
m4aips1: bus@41080000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x41080000 0x80000>;
|
|
ranges;
|
|
|
|
sim: sim@410a3000 {
|
|
compatible = "fsl,imx7ulp-sim", "syscon";
|
|
reg = <0x410a3000 0x1000>;
|
|
};
|
|
|
|
ocotp: ocotp-ctrl@410a6000 {
|
|
compatible = "fsl,imx7ulp-ocotp", "syscon";
|
|
reg = <0x410a6000 0x4000>;
|
|
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
|
|
};
|
|
};
|
|
};
|