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5d34d0b32d
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable. Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c A separate commit will adjust the clk-of-mmp2 driver. Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
224 lines
4.8 KiB
C
224 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
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int nr_clks)
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{
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struct clk **clk_table;
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clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_table)
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return;
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unit->clk_table = clk_table;
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unit->nr_clks = nr_clks;
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unit->clk_data.clks = clk_table;
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unit->clk_data.clk_num = nr_clks;
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of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
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}
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void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_rate_clk *clks,
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int size)
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{
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int i;
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struct clk *clk;
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for (i = 0; i < size; i++) {
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clk = clk_register_fixed_rate(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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clks[i].fixed_rate);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_factor_clk *clks,
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int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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clk = clk_register_fixed_factor(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags, clks[i].mult,
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clks[i].div);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_general_gate_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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clk = clk_register_gate(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].bit_idx,
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clks[i].gate_flags,
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clks[i].lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_gate_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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clk = mmp_clk_register_gate(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].mask,
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clks[i].val_enable,
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clks[i].val_disable,
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clks[i].gate_flags,
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clks[i].lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_mux_clks(struct mmp_clk_unit *unit,
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struct mmp_param_mux_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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clk = clk_register_mux(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].num_parents,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].shift,
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clks[i].width,
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clks[i].mux_flags,
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clks[i].lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_div_clks(struct mmp_clk_unit *unit,
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struct mmp_param_div_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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clk = clk_register_divider(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].shift,
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clks[i].width,
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clks[i].div_flags,
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clks[i].lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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void __iomem *reg = NULL;
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if (clks[i].offset)
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reg = base + clks[i].offset;
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clk = mmp_clk_register_pll(clks[i].name,
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clks[i].default_rate,
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base + clks[i].enable_offset,
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clks[i].enable,
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reg, clks[i].shift,
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clks[i].input_rate,
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base + clks[i].postdiv_offset,
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clks[i].postdiv_shift);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
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struct clk *clk)
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{
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if (IS_ERR_OR_NULL(clk)) {
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pr_err("CLK %d has invalid pointer %p\n", id, clk);
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return;
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}
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if (id >= unit->nr_clks) {
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pr_err("CLK %d is invalid\n", id);
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return;
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}
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unit->clk_table[id] = clk;
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}
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