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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bf75731dbc
Add the rpm clock controller node, to provide the low-noise baseband clock for the USB PHYs, among other things. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
850 lines
20 KiB
Plaintext
850 lines
20 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, Linaro Limited
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-qcs404", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0 0x80000000 0 0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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remoteproc_adsp: remoteproc-adsp {
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compatible = "qcom,qcs404-adsp-pas";
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interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&xo_board>;
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clock-names = "xo";
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memory-region = <&adsp_fw_mem>;
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qcom,smem-states = <&adsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
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qcom,remote-pid = <2>;
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mboxes = <&apcs_glb 8>;
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label = "adsp";
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};
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};
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remoteproc_cdsp: remoteproc-cdsp {
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compatible = "qcom,qcs404-cdsp-pas";
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interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&xo_board>;
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clock-names = "xo";
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memory-region = <&cdsp_fw_mem>;
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qcom,smem-states = <&cdsp_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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qcom,remote-pid = <5>;
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mboxes = <&apcs_glb 12>;
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label = "cdsp";
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};
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};
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remoteproc_wcss: remoteproc-wcss {
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compatible = "qcom,qcs404-wcss-pas";
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interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
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<&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&xo_board>;
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clock-names = "xo";
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memory-region = <&wlan_fw_mem>;
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qcom,smem-states = <&wcss_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
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qcom,remote-pid = <1>;
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mboxes = <&apcs_glb 16>;
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label = "wcss";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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memory@85600000 {
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reg = <0 0x85600000 0 0x90000>;
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no-map;
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};
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smem_region: memory@85f00000 {
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reg = <0 0x85f00000 0 0x200000>;
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no-map;
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};
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memory@86100000 {
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reg = <0 0x86100000 0 0x300000>;
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no-map;
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};
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wlan_fw_mem: memory@86400000 {
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reg = <0 0x86400000 0 0x1c00000>;
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no-map;
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};
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adsp_fw_mem: memory@88000000 {
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reg = <0 0x88000000 0 0x1a00000>;
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no-map;
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};
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cdsp_fw_mem: memory@89a00000 {
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reg = <0 0x89a00000 0 0x600000>;
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no-map;
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};
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wlan_msa_mem: memory@8a000000 {
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reg = <0 0x8a000000 0 0x100000>;
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no-map;
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};
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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rpm_requests: glink-channel {
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compatible = "qcom,rpm-qcs404";
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qcom,glink-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-qcs404";
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#clock-cells = <1>;
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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soc: soc@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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rpm_msg_ram: memory@60000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x00060000 0x6000>;
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};
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rng: rng@e3000 {
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compatible = "qcom,prng-ee";
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reg = <0x000e3000 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,qcs404-pinctrl";
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reg = <0x01000000 0x200000>,
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<0x01300000 0x200000>,
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<0x07b00000 0x200000>;
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reg-names = "south", "north", "east";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 120>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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blsp1_i2c0_default: blsp1-i2c0-default {
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pins = "gpio32", "gpio33";
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function = "blsp_i2c0";
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};
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blsp1_i2c1_default: blsp1-i2c1-default {
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pins = "gpio24", "gpio25";
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function = "blsp_i2c1";
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};
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blsp1_i2c2_default: blsp1-i2c2-default {
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sda {
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pins = "gpio19";
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function = "blsp_i2c_sda_a2";
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};
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scl {
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pins = "gpio20";
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function = "blsp_i2c_scl_a2";
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};
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};
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blsp1_i2c3_default: blsp1-i2c3-default {
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pins = "gpio84", "gpio85";
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function = "blsp_i2c3";
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};
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blsp1_i2c4_default: blsp1-i2c4-default {
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pins = "gpio117", "gpio118";
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function = "blsp_i2c4";
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};
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blsp1_uart0_default: blsp1-uart0-default {
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pins = "gpio30", "gpio31", "gpio32", "gpio33";
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function = "blsp_uart0";
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};
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blsp1_uart1_default: blsp1-uart1-default {
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pins = "gpio22", "gpio23";
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function = "blsp_uart1";
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};
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blsp1_uart2_default: blsp1-uart2-default {
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rx {
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pins = "gpio18";
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function = "blsp_uart_rx_a2";
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};
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tx {
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pins = "gpio17";
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function = "blsp_uart_tx_a2";
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};
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};
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blsp1_uart3_default: blsp1-uart3-default {
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pins = "gpio82", "gpio83", "gpio84", "gpio85";
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function = "blsp_uart3";
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};
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blsp2_i2c0_default: blsp2-i2c0-default {
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pins = "gpio28", "gpio29";
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function = "blsp_i2c5";
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};
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blsp1_spi0_default: blsp1-spi0-default {
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pins = "gpio30", "gpio31", "gpio32", "gpio33";
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function = "blsp_spi0";
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};
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blsp1_spi1_default: blsp1-spi1-default {
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pins = "gpio22", "gpio23", "gpio24", "gpio25";
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function = "blsp_spi1";
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};
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blsp1_spi2_default: blsp1-spi2-default {
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pins = "gpio17", "gpio18", "gpio19", "gpio20";
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function = "blsp_spi2";
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};
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blsp1_spi3_default: blsp1-spi3-default {
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pins = "gpio82", "gpio83", "gpio84", "gpio85";
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function = "blsp_spi3";
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};
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blsp1_spi4_default: blsp1-spi4-default {
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pins = "gpio37", "gpio38", "gpio117", "gpio118";
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function = "blsp_spi4";
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};
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blsp2_spi0_default: blsp2-spi0-default {
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pins = "gpio26", "gpio27", "gpio28", "gpio29";
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function = "blsp_spi5";
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};
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blsp2_uart0_default: blsp2-uart0-default {
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pins = "gpio26", "gpio27", "gpio28", "gpio29";
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function = "blsp_uart5";
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-qcs404";
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reg = <0x01800000 0x80000>;
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#clock-cells = <1>;
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assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
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assigned-clock-rates = <19200000>;
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};
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tcsr_mutex_regs: syscon@1905000 {
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compatible = "syscon";
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reg = <0x01905000 0x20000>;
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};
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spmi_bus: spmi@200f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0200f000 0x001000>,
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<0x02400000 0x800000>,
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<0x02c00000 0x800000>,
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<0x03800000 0x200000>,
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<0x0200a000 0x002100>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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sdcc1: sdcc@7804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
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reg-names = "hc_mem", "cmdq_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>,
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<&xo_board>;
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clock-names = "core", "iface", "xo";
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status = "disabled";
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};
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blsp1_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x25000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,controlled-remotely = <1>;
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qcom,ee = <0>;
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status = "okay";
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};
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blsp1_uart0: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_uart0_default>;
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status = "disabled";
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};
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blsp1_uart1: serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b0000 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_uart1_default>;
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status = "disabled";
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};
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blsp1_uart2: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&blsp1_uart2_default>;
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status = "okay";
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};
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wifi: wifi@a000000 {
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compatible = "qcom,wcn3990-wifi";
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reg = <0xa000000 0x800000>;
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reg-names = "membase";
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memory-region = <&wlan_msa_mem>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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|
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_uart3: serial@78b2000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x078b2000 0x200>;
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_uart3_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c0: i2c@78b5000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x078b5000 0x600>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_i2c0_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi0: spi@78b5000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b5000 0x600>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_spi0_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c1: i2c@78b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x078b6000 0x600>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_i2c1_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi1: spi@78b6000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b6000 0x600>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_spi1_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c2: i2c@78b7000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x078b7000 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_i2c2_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi2: spi@78b7000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b7000 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_spi2_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c3: i2c@78b8000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x078b8000 0x600>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_i2c3_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi3: spi@78b8000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b8000 0x600>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_spi3_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c4: i2c@78b9000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x078b9000 0x600>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_i2c4_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi4: spi@78b9000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b9000 0x600>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp1_spi4_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_dma: dma@7ac4000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x07ac4000 0x17000>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,controlled-remotely = <1>;
|
|
qcom,ee = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_uart0: serial@7aef000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x07aef000 0x200>;
|
|
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp2_uart0_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_i2c0: i2c@7af5000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x07af5000 0x600>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
|
<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp2_i2c0_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_spi0: spi@7af5000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x07af5000 0x600>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
|
|
<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&blsp2_spi0_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
intc: interrupt-controller@b000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0b000000 0x1000>,
|
|
<0x0b002000 0x1000>;
|
|
};
|
|
|
|
apcs_glb: mailbox@b011000 {
|
|
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
|
|
reg = <0x0b011000 0x1000>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
timer@b120000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0b120000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@b121000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b121000 0x1000>,
|
|
<0x0b122000 0x1000>;
|
|
};
|
|
|
|
frame@b123000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b124000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b125000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b126000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b127000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b128000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0b128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 0xff08>,
|
|
<GIC_PPI 3 0xff08>,
|
|
<GIC_PPI 4 0xff08>,
|
|
<GIC_PPI 1 0xff08>;
|
|
};
|
|
|
|
smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-wcss {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 18>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
wcss_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
wcss_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
};
|