linux_dsm_epyc7002/drivers/gpu/ipu-v3
Lucas Stach 11aff4b4c7 gpu: ipu-v3: pre: implement workaround for ERR009624
The PRE has a bug where a software write to the CTRL register can block
the setting of the ENABLE bit by the hardware in auto repeat mode. When
this happens the PRE will fail to handle new jobs. To work around this
software must not write to CTRL register when the PRE store engine is
inside the unsafe window, where a hardware update to the ENABLE bit
may happen.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
[p.zabel@pengutronix.de: rebased before PRE tiled prefetch support]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-11 12:04:24 +02:00
..
ipu-common.c gpu: ipu-v3: Allow channel burst locking on i.MX6 only 2017-10-11 10:45:06 +02:00
ipu-cpmem.c gpu: ipu-v3: Add support for double read/write reduction 2017-06-08 08:57:18 +02:00
ipu-csi.c gpu: ipu-v3: export ipu_csi_set_downsize 2017-02-17 08:04:27 +01:00
ipu-dc.c gpu: ipu-v3: remove IRQ dance on DC channel disable 2017-03-15 15:28:27 +01:00
ipu-di.c gpu: ipu-di: silence videomode logspam 2016-11-09 10:41:14 +01:00
ipu-dmfc.c gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel 2016-08-29 12:45:05 +02:00
ipu-dp.c drm/imx: add deferred plane disabling 2017-03-15 15:42:29 +01:00
ipu-ic.c gpu: ipu-v3: Add ipu_rot_mode_is_irt() 2016-09-19 08:30:14 +02:00
ipu-image-convert.c gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent 2017-03-16 10:14:49 +01:00
ipu-pre.c gpu: ipu-v3: pre: implement workaround for ERR009624 2017-10-11 12:04:24 +02:00
ipu-prg.c gpu: ipu-v3: prg: wait for double buffers to be filled on channel startup 2017-10-11 12:04:23 +02:00
ipu-prv.h gpu: ipu-v3: remove interrupt busy waiting routine 2017-06-08 08:57:19 +02:00
ipu-smfc.c
ipu-vdi.c gpu: ipu-v3: vdic: include AUTO field order bit in ipu_vdi_set_field_order 2017-06-08 08:57:20 +02:00
Kconfig gpu: ipu-v3: add DRM dependency 2017-08-11 10:31:13 +02:00
Makefile gpu: ipu-v3: don't depend on DRM being enabled 2017-04-04 10:58:56 +02:00