mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:59:33 +07:00
ae02e5d40d
This layer is responsible for - Enumerating over PCI bus - Inform FW about host readiness - Provide HW interface to transport layer for control and messages - Interrupt handling and routing Original-author: Daniel Drubin <daniel.drubin@intel.com> Reviewed-and-tested-by: Ooi, Joyce <joyce.ooi@intel.com> Tested-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Rann Bar-On <rb6@duke.edu> Tested-by: Atri Bhattacharya <badshah400@aim.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
31 lines
517 B
C
31 lines
517 B
C
#undef TRACE_SYSTEM
|
|
#define TRACE_SYSTEM intel_ish
|
|
|
|
#if !defined(_TRACE_INTEL_ISH_H) || defined(TRACE_HEADER_MULTI_READ)
|
|
#define _TRACE_INTEL_ISH_H
|
|
|
|
#include <linux/tracepoint.h>
|
|
|
|
TRACE_EVENT(ishtp_dump,
|
|
|
|
TP_PROTO(const char *message),
|
|
|
|
TP_ARGS(message),
|
|
|
|
TP_STRUCT__entry(
|
|
__string(message, message)
|
|
),
|
|
|
|
TP_fast_assign(
|
|
__assign_str(message, message);
|
|
),
|
|
|
|
TP_printk("%s", __get_str(message))
|
|
);
|
|
|
|
|
|
#endif /* _TRACE_INTEL_ISH_H */
|
|
|
|
/* This part must be outside protection */
|
|
#include <trace/define_trace.h>
|