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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8cdcd8aeee
This converts the two Freescale i.MX SPI drivers Freescale i.MX (CONFIG_SPI_IMX) and Freescale i.MX LPSPI (CONFIG_SPI_FSL_LPSPI) to use GPIO descriptors handled in the SPI core for GPIO chip selects whether defined in the device tree or a board file. The reason why both are converted at the same time is that they were both using the same platform data and platform device population helpers when using board files intertwining the code so this gives a cleaner cut. The platform device creation was passing a platform data container from each boardfile down to the driver using struct spi_imx_master from <linux/platform_data/spi-imx.h>, but this was only conveying the number of chipselects and an int * array of the chipselect GPIO numbers. The imx27 and imx31 platforms had code passing the now-unused platform data when creating the platform devices, this has been repurposed to pass around GPIO descriptor tables. The platform data struct that was just passing an array of integers and number of chip selects for the GPIO lines has been removed. The number of chipselects used to be passed from the board file, because this number also limits the number of native chipselects that the platform can use. To deal with this we just augment the i.MX (CONFIG_SPI_IMX) driver to support 3 chipselects if the platform does not define "num-cs" as a device property (such as from the device tree). This covers all the legacy boards as these use <= 3 native chip selects (or GPIO lines, and in that case the number of chip selects is determined by the core from the number of available GPIO lines). Any new boards should use device tree, so this is a reasonable simplification to cover all old boards. The LPSPI driver never assigned the number of chipselects and thus always fall back to the core default of 1 chip select if no GPIOs are defined in the device tree. The Freescale i.MX driver was already partly utilizing the SPI core to obtain the GPIO numbers from the device tree, so this completes the transtion to let the core handle all of it. All board files and the core i.MX boardfile registration code is augmented to account for these changes. This has been compile-tested with the imx_v4_v5_defconfig and the imx_v6_v7_defconfig. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Trent Piepho <tpiepho@impinj.com> Cc: Clark Wang <xiaoning.wang@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Link: https://lore.kernel.org/r/20200625200252.207614-1-linus.walleij@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
291 lines
7.2 KiB
C
291 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/moduleparam.h>
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#include <linux/smsc911x.h>
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#include <linux/mfd/mc13783.h>
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#include <linux/spi/spi.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ulpi.h>
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#include <linux/mtd/physmap.h>
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#include <linux/delay.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/fixed.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include "board-mx31lite.h"
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#include "common.h"
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#include "devices-imx31.h"
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#include "ehci.h"
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#include "hardware.h"
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#include "iomux-mx3.h"
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#include "ulpi.h"
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/*
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* This file contains the module-specific initialization routines.
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*/
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static unsigned int mx31lite_pins[] = {
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/* UART1 */
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MX31_PIN_CTS1__CTS1,
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MX31_PIN_RTS1__RTS1,
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MX31_PIN_TXD1__TXD1,
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MX31_PIN_RXD1__RXD1,
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/* SPI 0 */
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MX31_PIN_CSPI1_SCLK__SCLK,
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MX31_PIN_CSPI1_MOSI__MOSI,
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MX31_PIN_CSPI1_MISO__MISO,
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MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
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MX31_PIN_CSPI1_SS0__SS0,
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MX31_PIN_CSPI1_SS1__SS1,
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MX31_PIN_CSPI1_SS2__SS2,
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/* LAN9117 IRQ pin */
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IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
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/* SPI 1 */
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MX31_PIN_CSPI2_SCLK__SCLK,
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MX31_PIN_CSPI2_MOSI__MOSI,
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MX31_PIN_CSPI2_MISO__MISO,
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MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
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MX31_PIN_CSPI2_SS0__SS0,
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MX31_PIN_CSPI2_SS1__SS1,
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MX31_PIN_CSPI2_SS2__SS2,
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};
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/* UART */
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const struct mxc_nand_platform_data
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mx31lite_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct smsc911x_platform_config smsc911x_config = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.flags = SMSC911X_USE_16BIT,
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};
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static struct resource smsc911x_resources[] = {
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{
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.start = MX31_CS4_BASE_ADDR,
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.end = MX31_CS4_BASE_ADDR + 0x100,
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.flags = IORESOURCE_MEM,
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}, {
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/* irq number is run-time assigned */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smsc911x_device = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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static struct mc13xxx_platform_data mc13783_pdata __initdata = {
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.flags = MC13XXX_USE_RTC,
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};
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static struct spi_board_info mc13783_spi_dev __initdata = {
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.modalias = "mc13783",
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.max_speed_hz = 1000000,
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.bus_num = 1,
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.chip_select = 0,
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.platform_data = &mc13783_pdata,
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/* irq number is run-time assigned */
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};
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/*
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* USB
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*/
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#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
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PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
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static int usbh2_init(struct platform_device *pdev)
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{
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int pins[] = {
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MX31_PIN_USBH2_DATA0__USBH2_DATA0,
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MX31_PIN_USBH2_DATA1__USBH2_DATA1,
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MX31_PIN_USBH2_CLK__USBH2_CLK,
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MX31_PIN_USBH2_DIR__USBH2_DIR,
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MX31_PIN_USBH2_NXT__USBH2_NXT,
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MX31_PIN_USBH2_STP__USBH2_STP,
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};
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mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
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mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
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mxc_iomux_set_gpr(MUX_PGP_UH2, true);
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/* chip select */
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mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
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"USBH2_CS");
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gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
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gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
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mdelay(10);
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return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
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}
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static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
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.init = usbh2_init,
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.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
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};
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/*
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* NOR flash
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*/
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static struct physmap_flash_data nor_flash_data = {
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.width = 2,
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};
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static struct resource nor_flash_resource = {
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.start = 0xa0000000,
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.end = 0xa1ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device physmap_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &nor_flash_data,
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},
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.resource = &nor_flash_resource,
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.num_resources = 1,
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};
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/*
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* This structure defines the MX31 memory map.
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*/
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static struct map_desc mx31lite_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
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.length = MX31_CS4_SIZE,
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.type = MT_DEVICE
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}
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};
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/*
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* Set up static virtual mappings.
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*/
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static void __init mx31lite_map_io(void)
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{
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mx31_map_io();
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iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
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}
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static int mx31lite_baseboard;
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core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
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static struct regulator_consumer_supply dummy_supplies[] = {
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REGULATOR_SUPPLY("vdd33a", "smsc911x"),
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REGULATOR_SUPPLY("vddvario", "smsc911x"),
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};
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static void __init mx31lite_init(void)
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{
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imx31_soc_init();
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mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
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"mx31lite");
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imx31_add_imx_uart0(&uart_pdata);
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imx31_add_spi_imx0(NULL);
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/* NOR and NAND flash */
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platform_device_register(&physmap_flash_device);
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imx31_add_mxc_nand(&mx31lite_nand_board_info);
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imx31_add_spi_imx1(NULL);
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regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
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}
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static void __init mx31lite_late(void)
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{
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int ret;
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if (mx31lite_baseboard == MX31LITE_DB)
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mx31lite_db_init();
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mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
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spi_register_board_info(&mc13783_spi_dev, 1);
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/* USB */
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usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
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ULPI_OTG_DRVVBUS_EXT);
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if (usbh2_pdata.otg)
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imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
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/* SMSC9117 IRQ pin */
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ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
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if (ret)
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pr_warn("could not get LAN irq gpio\n");
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else {
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gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
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smsc911x_resources[1].start =
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gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
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smsc911x_resources[1].end =
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gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
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platform_device_register(&smsc911x_device);
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}
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}
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static void __init mx31lite_timer_init(void)
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{
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mx31_clocks_init(26000000);
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}
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MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
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/* Maintainer: Freescale Semiconductor, Inc. */
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.atag_offset = 0x100,
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.map_io = mx31lite_map_io,
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.init_early = imx31_init_early,
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.init_irq = mx31_init_irq,
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.init_time = mx31lite_timer_init,
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.init_machine = mx31lite_init,
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.init_late = mx31lite_late,
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.restart = mxc_restart,
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MACHINE_END
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