mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 23:25:23 +07:00
a7b2466cea
This patch updates the digital voltage levels from corner values to microvolts as we are going to use s1 regulator directly for vddcx instead of s1_corner. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
591 lines
14 KiB
Plaintext
591 lines
14 KiB
Plaintext
/*
|
|
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 and
|
|
* only version 2 as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
|
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. MSM8916";
|
|
compatible = "qcom,msm8916";
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
|
|
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
|
|
};
|
|
|
|
chosen { };
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
/* We expect the bootloader to fill in the reg */
|
|
reg = <0 0 0 0>;
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
reserve_aligned@86000000 {
|
|
reg = <0x0 0x86000000 0x0 0x0300000>;
|
|
no-map;
|
|
};
|
|
|
|
smem_mem: smem_region@86300000 {
|
|
reg = <0x0 0x86300000 0x0 0x0100000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x0>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x1>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x2>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0x3>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
L2_0: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
|
|
memory-region = <&smem_mem>;
|
|
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
|
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
soc: soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
restart@4ab000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0x4ab000 0x4>;
|
|
};
|
|
|
|
msmgpio: pinctrl@1000000 {
|
|
compatible = "qcom,msm8916-pinctrl";
|
|
reg = <0x1000000 0x300000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gcc: clock-controller@1800000 {
|
|
compatible = "qcom,gcc-msm8916";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
reg = <0x1800000 0x80000>;
|
|
};
|
|
|
|
tcsr_mutex_regs: syscon@1905000 {
|
|
compatible = "syscon";
|
|
reg = <0x1905000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_regs 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
rpm_msg_ram: memory@60000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x60000 0x8000>;
|
|
};
|
|
|
|
blsp1_uart1: serial@78af000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78af000 0x200>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 1>, <&blsp_dma 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
apcs: syscon@b011000 {
|
|
compatible = "syscon";
|
|
reg = <0x0b011000 0x1000>;
|
|
};
|
|
|
|
blsp1_uart2: serial@78b0000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78b0000 0x200>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 3>, <&blsp_dma 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_dma: dma@7884000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x07884000 0x23000>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi1: spi@78b5000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b5000 0x600>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 5>, <&blsp_dma 4>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi1_default>;
|
|
pinctrl-1 = <&spi1_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi2: spi@78b6000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b6000 0x600>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 7>, <&blsp_dma 6>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi2_default>;
|
|
pinctrl-1 = <&spi2_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi3: spi@78b7000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b7000 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 9>, <&blsp_dma 8>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi3_default>;
|
|
pinctrl-1 = <&spi3_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi4: spi@78b8000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b8000 0x600>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 11>, <&blsp_dma 10>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi4_default>;
|
|
pinctrl-1 = <&spi4_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi5: spi@78b9000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078b9000 0x600>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 13>, <&blsp_dma 12>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi5_default>;
|
|
pinctrl-1 = <&spi5_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_spi6: spi@78ba000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x078ba000 0x600>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
|
|
dma-names = "rx", "tx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi6_default>;
|
|
pinctrl-1 = <&spi6_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_i2c2: i2c@78b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x78b6000 0x1000>;
|
|
interrupts = <GIC_SPI 96 0>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c2_default>;
|
|
pinctrl-1 = <&i2c2_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_i2c4: i2c@78b8000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x78b8000 0x1000>;
|
|
interrupts = <GIC_SPI 98 0>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c4_default>;
|
|
pinctrl-1 = <&i2c4_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp_i2c6: i2c@78ba000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x78ba000 0x1000>;
|
|
interrupts = <GIC_SPI 100 0>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
|
|
clock-names = "iface", "core";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c6_default>;
|
|
pinctrl-1 = <&i2c6_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpass: lpass@07708000 {
|
|
status = "disabled";
|
|
compatible = "qcom,lpass-cpu-apq8016";
|
|
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
|
|
<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
|
|
<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
|
|
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
|
|
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
|
|
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
|
|
<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
|
|
|
|
clock-names = "ahbix-clk",
|
|
"pcnoc-mport-clk",
|
|
"pcnoc-sway-clk",
|
|
"mi2s-bit-clk0",
|
|
"mi2s-bit-clk1",
|
|
"mi2s-bit-clk2",
|
|
"mi2s-bit-clk3";
|
|
#sound-dai-cells = <1>;
|
|
|
|
interrupts = <0 160 0>;
|
|
interrupt-names = "lpass-irq-lpaif";
|
|
reg = <0x07708000 0x10000>;
|
|
reg-names = "lpass-lpaif";
|
|
};
|
|
|
|
sdhc_1: sdhci@07824000 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <0 123 0>, <0 138 0>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc_2: sdhci@07864000 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <0 125 0>, <0 221 0>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&gcc GCC_SDCC2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_dev: usb@78d9000 {
|
|
compatible = "qcom,ci-hdrc";
|
|
reg = <0x78d9000 0x400>;
|
|
dr_mode = "peripheral";
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
|
|
usb-phy = <&usb_otg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host: ehci@78d9000 {
|
|
compatible = "qcom,ehci-host";
|
|
reg = <0x78d9000 0x400>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
|
|
usb-phy = <&usb_otg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_otg: phy@78d9000 {
|
|
compatible = "qcom,usb-otg-snps";
|
|
reg = <0x78d9000 0x400>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
|
|
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
qcom,vdd-levels = <500000 1000000 1320000>;
|
|
qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
|
|
dr_mode = "peripheral";
|
|
qcom,otg-control = <2>; // PMIC
|
|
qcom,manual-pullup;
|
|
|
|
clocks = <&gcc GCC_USB_HS_AHB_CLK>,
|
|
<&gcc GCC_USB_HS_SYSTEM_CLK>,
|
|
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
|
|
clock-names = "iface", "core", "sleep";
|
|
|
|
resets = <&gcc GCC_USB2A_PHY_BCR>,
|
|
<&gcc GCC_USB_HS_BCR>;
|
|
reset-names = "phy", "link";
|
|
status = "disabled";
|
|
};
|
|
|
|
intc: interrupt-controller@b000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
|
};
|
|
|
|
timer@b020000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0xb020000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@b021000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb021000 0x1000>,
|
|
<0xb022000 0x1000>;
|
|
};
|
|
|
|
frame@b023000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb023000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b024000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb024000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b025000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb025000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b026000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb026000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b027000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb027000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@b028000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xb028000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spmi_bus: spmi@200f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x200f000 0x001000>,
|
|
<0x2400000 0x400000>,
|
|
<0x2c00000 0x400000>,
|
|
<0x3800000 0x200000>,
|
|
<0x200a000 0x002100>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
rng@22000 {
|
|
compatible = "qcom,prng";
|
|
reg = <0x00022000 0x200>;
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
clock-names = "core";
|
|
};
|
|
};
|
|
|
|
smd {
|
|
compatible = "qcom,smd";
|
|
|
|
rpm {
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 8 0>;
|
|
qcom,smd-edge = <15>;
|
|
|
|
rpm_requests {
|
|
compatible = "qcom,rpm-msm8916";
|
|
qcom,smd-channels = "rpm_requests";
|
|
|
|
rpmcc: qcom,rpmcc {
|
|
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smd_rpm_regulators: pm8916-regulators {
|
|
compatible = "qcom,rpm-pm8916-regulators";
|
|
|
|
pm8916_s1: s1 {};
|
|
pm8916_s3: s3 {};
|
|
pm8916_s4: s4 {};
|
|
|
|
pm8916_l1: l1 {};
|
|
pm8916_l2: l2 {};
|
|
pm8916_l3: l3 {};
|
|
pm8916_l4: l4 {};
|
|
pm8916_l5: l5 {};
|
|
pm8916_l6: l6 {};
|
|
pm8916_l7: l7 {};
|
|
pm8916_l8: l8 {};
|
|
pm8916_l9: l9 {};
|
|
pm8916_l10: l10 {};
|
|
pm8916_l11: l11 {};
|
|
pm8916_l12: l12 {};
|
|
pm8916_l13: l13 {};
|
|
pm8916_l14: l14 {};
|
|
pm8916_l15: l15 {};
|
|
pm8916_l16: l16 {};
|
|
pm8916_l17: l17 {};
|
|
pm8916_l18: l18 {};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "msm8916-pins.dtsi"
|