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5291925a9a
When we use > 4KB's page size the original definition is not consistent with PGDIR_SIZE. For exeample, if we use 16KB page size the PGDIR_SHIFT is (14-2) + 14 = 26, PGDIR_SIZE is 2^26，so the PTRS_PER_PGD should be: 2^32/2^26 = 2^6 but the original definition of PTRS_PER_PGD is 4096 (PGDIR_ORDER = 0). So, this definition needs to be consistent with the PGDIR_SIZE. And the new definition is consistent with the PGD init in pagetable_init(). Signed-off-by: Dajie Tan <jiankemeng@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
235 lines
7.5 KiB
C
235 lines
7.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PGTABLE_32_H
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#define _ASM_PGTABLE_32_H
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <linux/linkage.h>
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#include <asm/cachectl.h>
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#include <asm/fixmap.h>
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#include <asm-generic/pgtable-nopmd.h>
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/*
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* - add_wired_entry() add a fixed TLB entry, and move wired register
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*/
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extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/*
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* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
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* starting at the top and working down. This is for populating the
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* TLB before trap_init() puts the TLB miss handler in place. It
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* should be used only for entries matching the actual page tables,
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* to prevent inconsistencies.
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*/
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extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386. Some day
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* when we have proper page coloring support we can have a 1% quicker
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* tlb refill handling mechanism, but for now it is a bit slower but
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* works even with the cache aliasing problem the R4k and above have.
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*/
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use two-level, so
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* we don't really have any PUD/PMD directory physically.
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*/
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#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
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#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
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#define PUD_ORDER aieeee_attempt_to_allocate_pud
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#define PMD_ORDER 1
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#define PTE_ORDER 0
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#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
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#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
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#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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#define VMALLOC_START MAP_BASE
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#define PKMAP_BASE (0xfe000000UL)
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#endif
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#ifdef CONFIG_64BIT_PHYS_ADDR
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
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#else
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#endif
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern void load_pgd(unsigned long pg_dir);
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extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
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/*
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* Empty pgd/pmd entries point to the invalid_pte_table.
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*/
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == (unsigned long) invalid_pte_table;
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}
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#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
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static inline int pmd_present(pmd_t pmd)
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{
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return pmd_val(pmd) != (unsigned long) invalid_pte_table;
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
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}
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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static inline pte_t
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pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
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pte.pte_low = pgprot_val(prot);
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return pte;
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}
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#else
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#ifdef CONFIG_CPU_VR41XX
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#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
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#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
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#else
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#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
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#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#endif
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
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#define __pgd_offset(address) pgd_index(address)
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#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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/* to find an entry in a page-table-directory */
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#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
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/* Find an entry in the third-level page table.. */
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#define __pte_offset(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
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#define pte_offset_map_nested(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
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#define pte_unmap(pte) ((void)(pte))
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#define pte_unmap_nested(pte) ((void)(pte))
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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/* Swap entries must have VALID bit cleared. */
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#define __swp_type(x) (((x).val >> 10) & 0x1f)
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#define __swp_offset(x) ((x).val >> 15)
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#define __swp_entry(type,offset) \
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((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
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/*
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* Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
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*/
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#define PTE_FILE_MAX_BITS 28
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#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
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(((_pte).pte >> 2 ) & 0x38) | \
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(((_pte).pte >> 10) << 6 ))
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#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
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(((off) & 0x38) << 2 ) | \
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(((off) >> 6 ) << 10) | \
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_PAGE_FILE })
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#else
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define __swp_type(x) (((x).val >> 2) & 0x1f)
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#define __swp_offset(x) ((x).val >> 7)
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#define __swp_entry(type,offset) \
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((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
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#else
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#define __swp_type(x) (((x).val >> 8) & 0x1f)
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#define __swp_offset(x) ((x).val >> 13)
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#define __swp_entry(type,offset) \
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((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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/*
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* Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
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*/
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#define PTE_FILE_MAX_BITS 30
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#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
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#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
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#else
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/*
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* Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
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*/
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#define PTE_FILE_MAX_BITS 28
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#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
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(((_pte).pte >> 2) & 0x8) | \
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(((_pte).pte >> 8) << 4))
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#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
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(((off) & 0x8) << 2) | \
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(((off) >> 4) << 8) | \
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_PAGE_FILE })
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#endif
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#endif
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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#else
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#endif
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#endif /* _ASM_PGTABLE_32_H */
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