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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d4dc890b5
Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_CACHEFLUSH_H
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#define _ASM_POWERPC_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/cputable.h>
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/*
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* No cache flushing is required when address mappings are changed,
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* because the caches on PowerPCs are physically addressed.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void __flush_icache_range(unsigned long, unsigned long);
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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__flush_icache_range(start, stop);
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}
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void __flush_dcache_icache(void *page_va);
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extern void flush_dcache_icache_page(struct page *page);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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#ifdef CONFIG_PPC32
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extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC64
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extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
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#endif
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#ifdef CONFIG_DEBUG_PAGEALLOC
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/* internal debugging function */
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void kernel_map_pages(struct page *page, int numpages, int enable);
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHEFLUSH_H */
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