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8d8706e2f8
Run all rio files through indent -kr -i8 -bri0 -l255, as requested by Alan. rioboot.c and rioinit.c were skipped due to worrisome lindent warnings. Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/*
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** -----------------------------------------------------------------------------
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**
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** Perle Specialix driver for Linux
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** Ported from existing RIO Driver for SCO sources.
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*
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* (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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**
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** Module : board.h
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** SID : 1.2
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** Last Modified : 11/6/98 11:34:07
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** Retrieved : 11/6/98 11:34:20
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**
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** ident @(#)board.h 1.2
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**
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** -----------------------------------------------------------------------------
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*/
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#ifndef __rio_board_h__
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#define __rio_board_h__
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#ifdef SCCS_LABELS
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static char *_board_h_sccs_ = "@(#)board.h 1.2";
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#endif
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/*
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** board.h contains the definitions for the *hardware* of the host cards.
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** It describes the memory overlay for the dual port RAM area.
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*/
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#define DP_SRAM1_SIZE 0x7C00
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#define DP_SRAM2_SIZE 0x0200
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#define DP_SRAM3_SIZE 0x7000
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#define DP_SCRATCH_SIZE 0x1000
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#define DP_PARMMAP_ADDR 0x01FE /* offset into SRAM2 */
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#define DP_STARTUP_ADDR 0x01F8 /* offset into SRAM2 */
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/*
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** The shape of the Host Control area, at offset 0x7C00, Write Only
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*/
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struct s_Ctrl {
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BYTE DpCtl; /* 7C00 */
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BYTE Dp_Unused2_[127];
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BYTE DpIntSet; /* 7C80 */
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BYTE Dp_Unused3_[127];
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BYTE DpTpuReset; /* 7D00 */
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BYTE Dp_Unused4_[127];
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BYTE DpIntReset; /* 7D80 */
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BYTE Dp_Unused5_[127];
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};
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/*
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** The PROM data area on the host (0x7C00), Read Only
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*/
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struct s_Prom {
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WORD DpSlxCode[2];
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WORD DpRev;
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WORD Dp_Unused6_;
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WORD DpUniq[4];
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WORD DpJahre;
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WORD DpWoche;
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WORD DpHwFeature[5];
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WORD DpOemId;
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WORD DpSiggy[16];
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};
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/*
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** Union of the Ctrl and Prom areas
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*/
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union u_CtrlProm { /* This is the control/PROM area (0x7C00) */
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struct s_Ctrl DpCtrl;
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struct s_Prom DpProm;
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};
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/*
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** The top end of memory!
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*/
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struct s_ParmMapS { /* Area containing Parm Map Pointer */
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BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
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WORD DpParmMapAd;
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};
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struct s_StartUpS {
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BYTE Dp_Unused9_[DP_STARTUP_ADDR];
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BYTE Dp_LongJump[0x4];
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BYTE Dp_Unused10_[2];
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BYTE Dp_ShortJump[0x2];
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};
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union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
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BYTE DpSramMem[DP_SRAM2_SIZE];
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struct s_ParmMapS DpParmMapS;
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struct s_StartUpS DpStartUpS;
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};
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/*
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** This is the DP RAM overlay.
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*/
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struct DpRam {
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BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
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union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
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union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
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BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
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BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
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};
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#define DpControl DpCtrlProm.DpCtrl.DpCtl
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#define DpSetInt DpCtrlProm.DpCtrl.DpIntSet
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#define DpResetTpu DpCtrlProm.DpCtrl.DpTpuReset
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#define DpResetInt DpCtrlProm.DpCtrl.DpIntReset
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#define DpSlx DpCtrlProm.DpProm.DpSlxCode
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#define DpRevision DpCtrlProm.DpProm.DpRev
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#define DpUnique DpCtrlProm.DpProm.DpUniq
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#define DpYear DpCtrlProm.DpProm.DpJahre
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#define DpWeek DpCtrlProm.DpProm.DpWoche
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#define DpSignature DpCtrlProm.DpProm.DpSiggy
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#define DpParmMapR DpSram2ParmMap.DpParmMapS.DpParmMapAd
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#define DpSram2 DpSram2ParmMap.DpSramMem
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#endif
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