mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 08:06:39 +07:00
8aa6d4fc5f
Not used any more. Reviewed-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
864 lines
22 KiB
C
864 lines
22 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include <drm/drm_cache.h>
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#include "radeon.h"
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#include "radeon_trace.h"
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int radeon_ttm_init(struct radeon_device *rdev);
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void radeon_ttm_fini(struct radeon_device *rdev);
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static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
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/*
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* To exclude mutual BO access we rely on bo_reserve exclusion, as all
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* function are calling it.
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*/
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static void radeon_update_memory_usage(struct radeon_bo *bo,
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unsigned mem_type, int sign)
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{
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struct radeon_device *rdev = bo->rdev;
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u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
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switch (mem_type) {
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case TTM_PL_TT:
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if (sign > 0)
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atomic64_add(size, &rdev->gtt_usage);
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else
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atomic64_sub(size, &rdev->gtt_usage);
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break;
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case TTM_PL_VRAM:
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if (sign > 0)
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atomic64_add(size, &rdev->vram_usage);
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else
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atomic64_sub(size, &rdev->vram_usage);
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break;
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}
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}
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static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
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{
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struct radeon_bo *bo;
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bo = container_of(tbo, struct radeon_bo, tbo);
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radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
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mutex_lock(&bo->rdev->gem.mutex);
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list_del_init(&bo->list);
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mutex_unlock(&bo->rdev->gem.mutex);
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radeon_bo_clear_surface_reg(bo);
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WARN_ON(!list_empty(&bo->va));
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drm_gem_object_release(&bo->gem_base);
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kfree(bo);
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}
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bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
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{
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if (bo->destroy == &radeon_ttm_bo_destroy)
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return true;
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return false;
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}
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void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
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{
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u32 c = 0, i;
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rbo->placement.placement = rbo->placements;
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rbo->placement.busy_placement = rbo->placements;
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if (domain & RADEON_GEM_DOMAIN_VRAM) {
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/* Try placing BOs which don't need CPU access outside of the
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* CPU accessible part of VRAM
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*/
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if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
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rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
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rbo->placements[c].fpfn =
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rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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}
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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}
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if (domain & RADEON_GEM_DOMAIN_GTT) {
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if (rbo->flags & RADEON_GEM_GTT_UC) {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_TT;
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} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
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(rbo->rdev->flags & RADEON_IS_AGP)) {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_TT;
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} else {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
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TTM_PL_FLAG_TT;
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}
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}
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if (domain & RADEON_GEM_DOMAIN_CPU) {
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if (rbo->flags & RADEON_GEM_GTT_UC) {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_SYSTEM;
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} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
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rbo->rdev->flags & RADEON_IS_AGP) {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_SYSTEM;
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} else {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
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TTM_PL_FLAG_SYSTEM;
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}
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}
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if (!c) {
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rbo->placements[c].fpfn = 0;
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rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
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TTM_PL_FLAG_SYSTEM;
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}
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rbo->placement.num_placement = c;
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rbo->placement.num_busy_placement = c;
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for (i = 0; i < c; ++i) {
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if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
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(rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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!rbo->placements[i].fpfn)
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rbo->placements[i].lpfn =
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rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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else
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rbo->placements[i].lpfn = 0;
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}
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}
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int radeon_bo_create(struct radeon_device *rdev,
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unsigned long size, int byte_align, bool kernel,
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u32 domain, u32 flags, struct sg_table *sg,
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struct reservation_object *resv,
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struct radeon_bo **bo_ptr)
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{
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struct radeon_bo *bo;
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enum ttm_bo_type type;
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unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
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size_t acc_size;
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int r;
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size = ALIGN(size, PAGE_SIZE);
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else if (sg) {
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type = ttm_bo_type_sg;
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} else {
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type = ttm_bo_type_device;
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}
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*bo_ptr = NULL;
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acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
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sizeof(struct radeon_bo));
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bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
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if (unlikely(r)) {
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kfree(bo);
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return r;
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}
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bo->rdev = rdev;
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bo->surface_reg = -1;
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INIT_LIST_HEAD(&bo->list);
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INIT_LIST_HEAD(&bo->va);
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bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
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RADEON_GEM_DOMAIN_GTT |
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RADEON_GEM_DOMAIN_CPU);
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bo->flags = flags;
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/* PCI GART is always snooped */
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if (!(rdev->flags & RADEON_IS_PCIE))
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bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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/* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
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* See https://bugs.freedesktop.org/show_bug.cgi?id=91268
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*/
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if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
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bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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#ifdef CONFIG_X86_32
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/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
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* See https://bugs.freedesktop.org/show_bug.cgi?id=84627
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*/
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bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
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/* Don't try to enable write-combining when it can't work, or things
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* may be slow
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* See https://bugs.freedesktop.org/show_bug.cgi?id=88758
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*/
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#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
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thanks to write-combining
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if (bo->flags & RADEON_GEM_GTT_WC)
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DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
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"better performance thanks to write-combining\n");
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bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
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#else
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/* For architectures that don't support WC memory,
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* mask out the WC flag from the BO
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*/
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if (!drm_arch_can_wc_memory())
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bo->flags &= ~RADEON_GEM_GTT_WC;
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#endif
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radeon_ttm_placement_from_domain(bo, domain);
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/* Kernel allocation are uninterruptible */
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down_read(&rdev->pm.mclk_lock);
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r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
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&bo->placement, page_align, !kernel, NULL,
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acc_size, sg, resv, &radeon_ttm_bo_destroy);
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up_read(&rdev->pm.mclk_lock);
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if (unlikely(r != 0)) {
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return r;
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}
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*bo_ptr = bo;
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trace_radeon_bo_create(bo);
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return 0;
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}
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int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
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{
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bool is_iomem;
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int r;
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if (bo->kptr) {
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if (ptr) {
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*ptr = bo->kptr;
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}
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return 0;
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}
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r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
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if (r) {
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return r;
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}
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bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
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if (ptr) {
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*ptr = bo->kptr;
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}
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radeon_bo_check_tiling(bo, 0, 0);
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return 0;
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}
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void radeon_bo_kunmap(struct radeon_bo *bo)
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{
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if (bo->kptr == NULL)
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return;
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bo->kptr = NULL;
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radeon_bo_check_tiling(bo, 0, 0);
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ttm_bo_kunmap(&bo->kmap);
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}
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struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
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{
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if (bo == NULL)
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return NULL;
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ttm_bo_reference(&bo->tbo);
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return bo;
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}
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void radeon_bo_unref(struct radeon_bo **bo)
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{
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struct ttm_buffer_object *tbo;
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struct radeon_device *rdev;
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if ((*bo) == NULL)
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return;
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rdev = (*bo)->rdev;
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tbo = &((*bo)->tbo);
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ttm_bo_unref(&tbo);
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if (tbo == NULL)
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*bo = NULL;
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}
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int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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u64 *gpu_addr)
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{
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int r, i;
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if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
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return -EPERM;
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if (bo->pin_count) {
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bo->pin_count++;
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if (gpu_addr)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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if (max_offset != 0) {
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u64 domain_start;
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if (domain == RADEON_GEM_DOMAIN_VRAM)
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domain_start = bo->rdev->mc.vram_start;
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else
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domain_start = bo->rdev->mc.gtt_start;
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WARN_ON_ONCE(max_offset <
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(radeon_bo_gpu_offset(bo) - domain_start));
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}
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return 0;
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}
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radeon_ttm_placement_from_domain(bo, domain);
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for (i = 0; i < bo->placement.num_placement; i++) {
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/* force to pin into visible video ram */
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if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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!(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
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(!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
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bo->placements[i].lpfn =
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bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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else
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bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
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bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
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}
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (likely(r == 0)) {
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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if (domain == RADEON_GEM_DOMAIN_VRAM)
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bo->rdev->vram_pin_size += radeon_bo_size(bo);
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else
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bo->rdev->gart_pin_size += radeon_bo_size(bo);
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} else {
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dev_err(bo->rdev->dev, "%p pin failed\n", bo);
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}
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return r;
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}
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int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
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{
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return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
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}
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int radeon_bo_unpin(struct radeon_bo *bo)
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{
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int r, i;
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if (!bo->pin_count) {
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dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
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return 0;
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}
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bo->pin_count--;
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if (bo->pin_count)
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return 0;
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for (i = 0; i < bo->placement.num_placement; i++) {
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bo->placements[i].lpfn = 0;
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bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
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}
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (likely(r == 0)) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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bo->rdev->vram_pin_size -= radeon_bo_size(bo);
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else
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bo->rdev->gart_pin_size -= radeon_bo_size(bo);
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} else {
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dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
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}
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return r;
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}
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int radeon_bo_evict_vram(struct radeon_device *rdev)
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{
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/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
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if (0 && (rdev->flags & RADEON_IS_IGP)) {
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if (rdev->mc.igp_sideport_enabled == false)
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/* Useless to evict on IGP chips */
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return 0;
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}
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return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
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}
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void radeon_bo_force_delete(struct radeon_device *rdev)
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{
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struct radeon_bo *bo, *n;
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if (list_empty(&rdev->gem.objects)) {
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return;
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}
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dev_err(rdev->dev, "Userspace still has active objects !\n");
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list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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dev_err(rdev->dev, "%p %p %lu %lu force free\n",
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&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
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*((unsigned long *)&bo->gem_base.refcount));
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mutex_lock(&bo->rdev->gem.mutex);
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list_del_init(&bo->list);
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mutex_unlock(&bo->rdev->gem.mutex);
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/* this should unref the ttm bo */
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drm_gem_object_unreference_unlocked(&bo->gem_base);
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}
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}
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int radeon_bo_init(struct radeon_device *rdev)
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{
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/* Add an MTRR for the VRAM */
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if (!rdev->fastfb_working) {
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rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
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rdev->mc.aper_size);
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}
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DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
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rdev->mc.mc_vram_size >> 20,
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(unsigned long long)rdev->mc.aper_size >> 20);
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DRM_INFO("RAM width %dbits %cDR\n",
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rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
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return radeon_ttm_init(rdev);
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|
}
|
|
|
|
void radeon_bo_fini(struct radeon_device *rdev)
|
|
{
|
|
radeon_ttm_fini(rdev);
|
|
arch_phys_wc_del(rdev->mc.vram_mtrr);
|
|
}
|
|
|
|
/* Returns how many bytes TTM can move per IB.
|
|
*/
|
|
static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
|
|
{
|
|
u64 real_vram_size = rdev->mc.real_vram_size;
|
|
u64 vram_usage = atomic64_read(&rdev->vram_usage);
|
|
|
|
/* This function is based on the current VRAM usage.
|
|
*
|
|
* - If all of VRAM is free, allow relocating the number of bytes that
|
|
* is equal to 1/4 of the size of VRAM for this IB.
|
|
|
|
* - If more than one half of VRAM is occupied, only allow relocating
|
|
* 1 MB of data for this IB.
|
|
*
|
|
* - From 0 to one half of used VRAM, the threshold decreases
|
|
* linearly.
|
|
* __________________
|
|
* 1/4 of -|\ |
|
|
* VRAM | \ |
|
|
* | \ |
|
|
* | \ |
|
|
* | \ |
|
|
* | \ |
|
|
* | \ |
|
|
* | \________|1 MB
|
|
* |----------------|
|
|
* VRAM 0 % 100 %
|
|
* used used
|
|
*
|
|
* Note: It's a threshold, not a limit. The threshold must be crossed
|
|
* for buffer relocations to stop, so any buffer of an arbitrary size
|
|
* can be moved as long as the threshold isn't crossed before
|
|
* the relocation takes place. We don't want to disable buffer
|
|
* relocations completely.
|
|
*
|
|
* The idea is that buffers should be placed in VRAM at creation time
|
|
* and TTM should only do a minimum number of relocations during
|
|
* command submission. In practice, you need to submit at least
|
|
* a dozen IBs to move all buffers to VRAM if they are in GTT.
|
|
*
|
|
* Also, things can get pretty crazy under memory pressure and actual
|
|
* VRAM usage can change a lot, so playing safe even at 50% does
|
|
* consistently increase performance.
|
|
*/
|
|
|
|
u64 half_vram = real_vram_size >> 1;
|
|
u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
|
|
u64 bytes_moved_threshold = half_free_vram >> 1;
|
|
return max(bytes_moved_threshold, 1024*1024ull);
|
|
}
|
|
|
|
int radeon_bo_list_validate(struct radeon_device *rdev,
|
|
struct ww_acquire_ctx *ticket,
|
|
struct list_head *head, int ring)
|
|
{
|
|
struct radeon_bo_list *lobj;
|
|
struct list_head duplicates;
|
|
int r;
|
|
u64 bytes_moved = 0, initial_bytes_moved;
|
|
u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
|
|
|
|
INIT_LIST_HEAD(&duplicates);
|
|
r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
|
|
if (unlikely(r != 0)) {
|
|
return r;
|
|
}
|
|
|
|
list_for_each_entry(lobj, head, tv.head) {
|
|
struct radeon_bo *bo = lobj->robj;
|
|
if (!bo->pin_count) {
|
|
u32 domain = lobj->prefered_domains;
|
|
u32 allowed = lobj->allowed_domains;
|
|
u32 current_domain =
|
|
radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
|
|
|
|
/* Check if this buffer will be moved and don't move it
|
|
* if we have moved too many buffers for this IB already.
|
|
*
|
|
* Note that this allows moving at least one buffer of
|
|
* any size, because it doesn't take the current "bo"
|
|
* into account. We don't want to disallow buffer moves
|
|
* completely.
|
|
*/
|
|
if ((allowed & current_domain) != 0 &&
|
|
(domain & current_domain) == 0 && /* will be moved */
|
|
bytes_moved > bytes_moved_threshold) {
|
|
/* don't move it */
|
|
domain = current_domain;
|
|
}
|
|
|
|
retry:
|
|
radeon_ttm_placement_from_domain(bo, domain);
|
|
if (ring == R600_RING_TYPE_UVD_INDEX)
|
|
radeon_uvd_force_into_uvd_segment(bo, allowed);
|
|
|
|
initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
|
|
bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
|
|
initial_bytes_moved;
|
|
|
|
if (unlikely(r)) {
|
|
if (r != -ERESTARTSYS &&
|
|
domain != lobj->allowed_domains) {
|
|
domain = lobj->allowed_domains;
|
|
goto retry;
|
|
}
|
|
ttm_eu_backoff_reservation(ticket, head);
|
|
return r;
|
|
}
|
|
}
|
|
lobj->gpu_offset = radeon_bo_gpu_offset(bo);
|
|
lobj->tiling_flags = bo->tiling_flags;
|
|
}
|
|
|
|
list_for_each_entry(lobj, &duplicates, tv.head) {
|
|
lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
|
|
lobj->tiling_flags = lobj->robj->tiling_flags;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int radeon_bo_get_surface_reg(struct radeon_bo *bo)
|
|
{
|
|
struct radeon_device *rdev = bo->rdev;
|
|
struct radeon_surface_reg *reg;
|
|
struct radeon_bo *old_object;
|
|
int steal;
|
|
int i;
|
|
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
if (!bo->tiling_flags)
|
|
return 0;
|
|
|
|
if (bo->surface_reg >= 0) {
|
|
reg = &rdev->surface_regs[bo->surface_reg];
|
|
i = bo->surface_reg;
|
|
goto out;
|
|
}
|
|
|
|
steal = -1;
|
|
for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
|
|
|
|
reg = &rdev->surface_regs[i];
|
|
if (!reg->bo)
|
|
break;
|
|
|
|
old_object = reg->bo;
|
|
if (old_object->pin_count == 0)
|
|
steal = i;
|
|
}
|
|
|
|
/* if we are all out */
|
|
if (i == RADEON_GEM_MAX_SURFACES) {
|
|
if (steal == -1)
|
|
return -ENOMEM;
|
|
/* find someone with a surface reg and nuke their BO */
|
|
reg = &rdev->surface_regs[steal];
|
|
old_object = reg->bo;
|
|
/* blow away the mapping */
|
|
DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
|
|
ttm_bo_unmap_virtual(&old_object->tbo);
|
|
old_object->surface_reg = -1;
|
|
i = steal;
|
|
}
|
|
|
|
bo->surface_reg = i;
|
|
reg->bo = bo;
|
|
|
|
out:
|
|
radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
|
|
bo->tbo.mem.start << PAGE_SHIFT,
|
|
bo->tbo.num_pages << PAGE_SHIFT);
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
|
|
{
|
|
struct radeon_device *rdev = bo->rdev;
|
|
struct radeon_surface_reg *reg;
|
|
|
|
if (bo->surface_reg == -1)
|
|
return;
|
|
|
|
reg = &rdev->surface_regs[bo->surface_reg];
|
|
radeon_clear_surface_reg(rdev, bo->surface_reg);
|
|
|
|
reg->bo = NULL;
|
|
bo->surface_reg = -1;
|
|
}
|
|
|
|
int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
|
|
uint32_t tiling_flags, uint32_t pitch)
|
|
{
|
|
struct radeon_device *rdev = bo->rdev;
|
|
int r;
|
|
|
|
if (rdev->family >= CHIP_CEDAR) {
|
|
unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
|
|
|
|
bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
|
|
bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
|
|
mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
|
|
tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
|
|
stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
|
|
switch (bankw) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
switch (bankh) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
switch (mtaspect) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
if (tilesplit > 6) {
|
|
return -EINVAL;
|
|
}
|
|
if (stilesplit > 6) {
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
r = radeon_bo_reserve(bo, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
bo->tiling_flags = tiling_flags;
|
|
bo->pitch = pitch;
|
|
radeon_bo_unreserve(bo);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
|
|
uint32_t *tiling_flags,
|
|
uint32_t *pitch)
|
|
{
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
if (tiling_flags)
|
|
*tiling_flags = bo->tiling_flags;
|
|
if (pitch)
|
|
*pitch = bo->pitch;
|
|
}
|
|
|
|
int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
|
|
bool force_drop)
|
|
{
|
|
if (!force_drop)
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
|
|
return 0;
|
|
|
|
if (force_drop) {
|
|
radeon_bo_clear_surface_reg(bo);
|
|
return 0;
|
|
}
|
|
|
|
if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
|
|
if (!has_moved)
|
|
return 0;
|
|
|
|
if (bo->surface_reg >= 0)
|
|
radeon_bo_clear_surface_reg(bo);
|
|
return 0;
|
|
}
|
|
|
|
if ((bo->surface_reg >= 0) && !has_moved)
|
|
return 0;
|
|
|
|
return radeon_bo_get_surface_reg(bo);
|
|
}
|
|
|
|
void radeon_bo_move_notify(struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *new_mem)
|
|
{
|
|
struct radeon_bo *rbo;
|
|
|
|
if (!radeon_ttm_bo_is_radeon_bo(bo))
|
|
return;
|
|
|
|
rbo = container_of(bo, struct radeon_bo, tbo);
|
|
radeon_bo_check_tiling(rbo, 0, 1);
|
|
radeon_vm_bo_invalidate(rbo->rdev, rbo);
|
|
|
|
/* update statistics */
|
|
if (!new_mem)
|
|
return;
|
|
|
|
radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
|
|
radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
|
|
}
|
|
|
|
int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct radeon_bo *rbo;
|
|
unsigned long offset, size, lpfn;
|
|
int i, r;
|
|
|
|
if (!radeon_ttm_bo_is_radeon_bo(bo))
|
|
return 0;
|
|
rbo = container_of(bo, struct radeon_bo, tbo);
|
|
radeon_bo_check_tiling(rbo, 0, 0);
|
|
rdev = rbo->rdev;
|
|
if (bo->mem.mem_type != TTM_PL_VRAM)
|
|
return 0;
|
|
|
|
size = bo->mem.num_pages << PAGE_SHIFT;
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
if ((offset + size) <= rdev->mc.visible_vram_size)
|
|
return 0;
|
|
|
|
/* Can't move a pinned BO to visible VRAM */
|
|
if (rbo->pin_count > 0)
|
|
return -EINVAL;
|
|
|
|
/* hurrah the memory is not visible ! */
|
|
radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
|
|
lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
|
|
for (i = 0; i < rbo->placement.num_placement; i++) {
|
|
/* Force into visible VRAM */
|
|
if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
|
|
(!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
|
|
rbo->placements[i].lpfn = lpfn;
|
|
}
|
|
r = ttm_bo_validate(bo, &rbo->placement, false, false);
|
|
if (unlikely(r == -ENOMEM)) {
|
|
radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
|
|
return ttm_bo_validate(bo, &rbo->placement, false, false);
|
|
} else if (unlikely(r != 0)) {
|
|
return r;
|
|
}
|
|
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
/* this should never happen */
|
|
if ((offset + size) > rdev->mc.visible_vram_size)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
|
|
{
|
|
int r;
|
|
|
|
r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
if (mem_type)
|
|
*mem_type = bo->tbo.mem.mem_type;
|
|
|
|
r = ttm_bo_wait(&bo->tbo, true, no_wait);
|
|
ttm_bo_unreserve(&bo->tbo);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* radeon_bo_fence - add fence to buffer object
|
|
*
|
|
* @bo: buffer object in question
|
|
* @fence: fence to add
|
|
* @shared: true if fence should be added shared
|
|
*
|
|
*/
|
|
void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
|
|
bool shared)
|
|
{
|
|
struct reservation_object *resv = bo->tbo.resv;
|
|
|
|
if (shared)
|
|
reservation_object_add_shared_fence(resv, &fence->base);
|
|
else
|
|
reservation_object_add_excl_fence(resv, &fence->base);
|
|
}
|