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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3cf8bb1ad1
I hate doing this but it hurts my eyes to go over code that does not comply with indentation rules. Only thing that is not only space change is in atom.c all other files are space indentation issues. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
536 lines
15 KiB
C
536 lines
15 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#include <linux/hdmi.h>
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#include <linux/gcd.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_audio.h"
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#include "r600d.h"
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#include "atom.h"
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/*
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* HDMI color format
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*/
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enum r600_hdmi_color_format {
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RGB = 0,
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YCC_422 = 1,
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YCC_444 = 2
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};
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/*
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* IEC60958 status bits
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*/
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enum r600_hdmi_iec_status_bits {
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AUDIO_STATUS_DIG_ENABLE = 0x01,
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AUDIO_STATUS_V = 0x02,
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AUDIO_STATUS_VCFG = 0x04,
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AUDIO_STATUS_EMPHASIS = 0x08,
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AUDIO_STATUS_COPYRIGHT = 0x10,
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AUDIO_STATUS_NONAUDIO = 0x20,
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AUDIO_STATUS_PROFESSIONAL = 0x40,
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AUDIO_STATUS_LEVEL = 0x80
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};
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static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
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{
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struct r600_audio_pin status;
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uint32_t value;
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value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
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/* number of channels */
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status.channels = (value & 0x7) + 1;
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/* bits per sample */
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switch ((value & 0xF0) >> 4) {
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case 0x0:
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status.bits_per_sample = 8;
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break;
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case 0x1:
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status.bits_per_sample = 16;
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break;
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case 0x2:
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status.bits_per_sample = 20;
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break;
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case 0x3:
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status.bits_per_sample = 24;
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break;
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case 0x4:
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status.bits_per_sample = 32;
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break;
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default:
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dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
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(int)value);
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status.bits_per_sample = 16;
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}
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/* current sampling rate in HZ */
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if (value & 0x4000)
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status.rate = 44100;
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else
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status.rate = 48000;
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status.rate *= ((value >> 11) & 0x7) + 1;
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status.rate /= ((value >> 8) & 0x7) + 1;
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value = RREG32(R600_AUDIO_STATUS_BITS);
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/* iec 60958 status bits */
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status.status_bits = value & 0xff;
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/* iec 60958 category code */
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status.category_code = (value >> 8) & 0xff;
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return status;
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}
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/*
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* update all hdmi interfaces with current audio parameters
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*/
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void r600_audio_update_hdmi(struct work_struct *work)
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{
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struct radeon_device *rdev = container_of(work, struct radeon_device,
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audio_work);
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struct drm_device *dev = rdev->ddev;
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struct r600_audio_pin audio_status = r600_audio_status(rdev);
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struct drm_encoder *encoder;
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bool changed = false;
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if (rdev->audio.pin[0].channels != audio_status.channels ||
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rdev->audio.pin[0].rate != audio_status.rate ||
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rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
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rdev->audio.pin[0].status_bits != audio_status.status_bits ||
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rdev->audio.pin[0].category_code != audio_status.category_code) {
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rdev->audio.pin[0] = audio_status;
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changed = true;
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (!radeon_encoder_is_digital(encoder))
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continue;
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if (changed || r600_hdmi_buffer_status_changed(encoder))
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r600_hdmi_update_audio_settings(encoder);
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}
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}
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/* enable the audio stream */
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void r600_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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u8 enable_mask)
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{
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u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
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if (!pin)
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return;
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if (enable_mask) {
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tmp |= AUDIO_ENABLED;
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if (enable_mask & 1)
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tmp |= PIN0_AUDIO_ENABLED;
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if (enable_mask & 2)
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tmp |= PIN1_AUDIO_ENABLED;
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if (enable_mask & 4)
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tmp |= PIN2_AUDIO_ENABLED;
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if (enable_mask & 8)
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tmp |= PIN3_AUDIO_ENABLED;
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} else {
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tmp &= ~(AUDIO_ENABLED |
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PIN0_AUDIO_ENABLED |
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PIN1_AUDIO_ENABLED |
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PIN2_AUDIO_ENABLED |
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PIN3_AUDIO_ENABLED);
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}
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WREG32(AZ_HOT_PLUG_CONTROL, tmp);
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}
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struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
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{
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/* only one pin on 6xx-NI */
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return &rdev->audio.pin[0];
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}
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void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
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const struct radeon_hdmi_acr *acr)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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/* DCE 3.0 uses register that's normally for CRC_CONTROL */
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uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
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HDMI0_ACR_PACKET_CONTROL;
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WREG32_P(acr_ctl + offset,
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HDMI0_ACR_SOURCE | /* select SW CTS value */
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HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
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~(HDMI0_ACR_SOURCE |
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HDMI0_ACR_AUTO_SEND));
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WREG32_P(HDMI0_ACR_32_0 + offset,
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HDMI0_ACR_CTS_32(acr->cts_32khz),
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~HDMI0_ACR_CTS_32_MASK);
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WREG32_P(HDMI0_ACR_32_1 + offset,
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HDMI0_ACR_N_32(acr->n_32khz),
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~HDMI0_ACR_N_32_MASK);
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WREG32_P(HDMI0_ACR_44_0 + offset,
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HDMI0_ACR_CTS_44(acr->cts_44_1khz),
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~HDMI0_ACR_CTS_44_MASK);
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WREG32_P(HDMI0_ACR_44_1 + offset,
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HDMI0_ACR_N_44(acr->n_44_1khz),
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~HDMI0_ACR_N_44_MASK);
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WREG32_P(HDMI0_ACR_48_0 + offset,
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HDMI0_ACR_CTS_48(acr->cts_48khz),
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~HDMI0_ACR_CTS_48_MASK);
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WREG32_P(HDMI0_ACR_48_1 + offset,
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HDMI0_ACR_N_48(acr->n_48khz),
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~HDMI0_ACR_N_48_MASK);
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}
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/*
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* build a HDMI Video Info Frame
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*/
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void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
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unsigned char *buffer, size_t size)
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{
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uint8_t *frame = buffer + 3;
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WREG32(HDMI0_AVI_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(HDMI0_AVI_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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WREG32(HDMI0_AVI_INFO2 + offset,
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frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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WREG32(HDMI0_AVI_INFO3 + offset,
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frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
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WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */
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WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */
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}
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/*
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* build a Audio Info Frame
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*/
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static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
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const void *buffer, size_t size)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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const u8 *frame = buffer + 3;
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WREG32(HDMI0_AUDIO_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(HDMI0_AUDIO_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
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}
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/*
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* test if audio buffer is filled enough to start playing
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*/
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static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
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}
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/*
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* have buffer status changed since last call?
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*/
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int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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int status, result;
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if (!dig->afmt || !dig->afmt->enabled)
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return 0;
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status = r600_hdmi_is_audio_buffer_filled(encoder);
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result = dig->afmt->last_buffer_filled_status != status;
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dig->afmt->last_buffer_filled_status = status;
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return result;
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}
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/*
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* write the audio workaround status to the hardware
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*/
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void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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uint32_t offset = dig->afmt->offset;
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bool hdmi_audio_workaround = false; /* FIXME */
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u32 value;
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if (!hdmi_audio_workaround ||
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r600_hdmi_is_audio_buffer_filled(encoder))
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value = 0; /* disable workaround */
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else
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value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
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WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
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value, ~HDMI0_AUDIO_TEST_EN);
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}
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void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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struct radeon_encoder *radeon_encoder;
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struct radeon_encoder_atom_dig *dig;
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if (!crtc)
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return;
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radeon_encoder = to_radeon_encoder(crtc->encoder);
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dig = radeon_encoder->enc_priv;
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if (!dig)
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return;
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if (dig->dig_encoder == 0) {
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WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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} else {
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WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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}
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void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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HDMI0_GC_SEND | /* send general control packets */
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HDMI0_GC_CONT); /* send general control packets every frame */
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}
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void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
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HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
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~(HDMI0_AUDIO_SAMPLE_SEND |
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HDMI0_AUDIO_DELAY_EN_MASK |
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HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
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HDMI0_60958_CS_UPDATE));
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WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
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HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
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WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
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HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
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~HDMI0_AUDIO_INFO_LINE_MASK);
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WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
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~(HDMI0_GENERIC0_SEND |
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HDMI0_GENERIC0_CONT |
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HDMI0_GENERIC0_UPDATE |
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HDMI0_GENERIC1_SEND |
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HDMI0_GENERIC1_CONT |
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HDMI0_GENERIC0_LINE_MASK |
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HDMI0_GENERIC1_LINE_MASK));
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WREG32_P(HDMI0_60958_0 + offset,
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HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
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~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
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HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
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WREG32_P(HDMI0_60958_1 + offset,
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HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
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~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
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}
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void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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if (mute)
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WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
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else
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WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
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}
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/**
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* r600_hdmi_update_audio_settings - Update audio infoframe
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*
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* @encoder: drm encoder
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*
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* Gets info about current audio stream and updates audio infoframe.
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*/
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void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct r600_audio_pin audio = r600_audio_status(rdev);
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uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
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struct hdmi_audio_infoframe frame;
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uint32_t offset;
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uint32_t value;
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ssize_t err;
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if (!dig->afmt || !dig->afmt->enabled)
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return;
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offset = dig->afmt->offset;
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DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
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r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
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audio.channels, audio.rate, audio.bits_per_sample);
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DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
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(int)audio.status_bits, (int)audio.category_code);
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err = hdmi_audio_infoframe_init(&frame);
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if (err < 0) {
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DRM_ERROR("failed to setup audio infoframe\n");
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return;
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}
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frame.channels = audio.channels;
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err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
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if (err < 0) {
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DRM_ERROR("failed to pack audio infoframe\n");
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return;
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}
|
|
|
|
value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
|
|
if (value & HDMI0_AUDIO_TEST_EN)
|
|
WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
|
|
value & ~HDMI0_AUDIO_TEST_EN);
|
|
|
|
WREG32_OR(HDMI0_CONTROL + offset,
|
|
HDMI0_ERROR_ACK);
|
|
|
|
WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
|
|
~HDMI0_AUDIO_INFO_SOURCE);
|
|
|
|
r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
|
|
|
|
WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
|
|
HDMI0_AUDIO_INFO_CONT |
|
|
HDMI0_AUDIO_INFO_UPDATE);
|
|
}
|
|
|
|
/*
|
|
* enable the HDMI engine
|
|
*/
|
|
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
u32 hdmi = HDMI0_ERROR_ACK;
|
|
|
|
if (!dig || !dig->afmt)
|
|
return;
|
|
|
|
/* Older chipsets require setting HDMI and routing manually */
|
|
if (!ASIC_IS_DCE3(rdev)) {
|
|
if (enable)
|
|
hdmi |= HDMI0_ENABLE;
|
|
switch (radeon_encoder->encoder_id) {
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
|
|
if (enable) {
|
|
WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
|
|
} else {
|
|
WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
|
|
}
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
|
|
if (enable) {
|
|
WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
|
|
} else {
|
|
WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
|
|
}
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_DDI:
|
|
if (enable) {
|
|
WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
|
|
} else {
|
|
WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
|
|
}
|
|
break;
|
|
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
|
|
if (enable)
|
|
hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
|
|
break;
|
|
default:
|
|
dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
|
|
radeon_encoder->encoder_id);
|
|
break;
|
|
}
|
|
WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
|
|
}
|
|
|
|
if (rdev->irq.installed) {
|
|
/* if irq is available use it */
|
|
/* XXX: shouldn't need this on any asics. Double check DCE2/3 */
|
|
if (enable)
|
|
radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
|
|
else
|
|
radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
|
|
}
|
|
|
|
dig->afmt->enabled = enable;
|
|
|
|
DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
|
|
enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
|
|
}
|
|
|