mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-08 13:36:42 +07:00
91c8a326a1
Since drm_i915_private is now a subclass of drm_device we do not need to
chase the drm_i915_private->dev backpointer and can instead simply
access drm_i915_private->drm directly.
text data bss dec hex filename
1068757
4565 416 1073738 10624a drivers/gpu/drm/i915/i915.ko
1066949 4565 416 1071930 105b3a drivers/gpu/drm/i915/i915.ko
Created by the coccinelle script:
@@
struct drm_i915_private *d;
identifier i;
@@
(
- d->dev->i
+ d->drm.i
|
- d->dev
+ &d->drm
)
and for good measure the dev_priv->dev backpointer was removed entirely.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467711623-2905-4-git-send-email-chris@chris-wilson.co.uk
1134 lines
31 KiB
C
1134 lines
31 KiB
C
/*
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* Copyright © 2011-2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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/*
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* This file implements HW context support. On gen5+ a HW context consists of an
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* opaque GPU object which is referenced at times of context saves and restores.
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* With RC6 enabled, the context is also referenced as the GPU enters and exists
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* from RC6 (GPU has it's own internal power context, except on gen5). Though
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* something like a context does exist for the media ring, the code only
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* supports contexts for the render ring.
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*
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* In software, there is a distinction between contexts created by the user,
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* and the default HW context. The default HW context is used by GPU clients
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* that do not request setup of their own hardware context. The default
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* context's state is never restored to help prevent programming errors. This
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* would happen if a client ran and piggy-backed off another clients GPU state.
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* The default context only exists to give the GPU some offset to load as the
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* current to invoke a save of the context we actually care about. In fact, the
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* code could likely be constructed, albeit in a more complicated fashion, to
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* never use the default context, though that limits the driver's ability to
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* swap out, and/or destroy other contexts.
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*
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* All other contexts are created as a request by the GPU client. These contexts
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* store GPU state, and thus allow GPU clients to not re-emit state (and
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* potentially query certain state) at any time. The kernel driver makes
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* certain that the appropriate commands are inserted.
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*
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* The context life cycle is semi-complicated in that context BOs may live
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* longer than the context itself because of the way the hardware, and object
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* tracking works. Below is a very crude representation of the state machine
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* describing the context life.
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* refcount pincount active
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* S0: initial state 0 0 0
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* S1: context created 1 0 0
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* S2: context is currently running 2 1 X
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* S3: GPU referenced, but not current 2 0 1
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* S4: context is current, but destroyed 1 1 0
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* S5: like S3, but destroyed 1 0 1
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*
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* The most common (but not all) transitions:
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* S0->S1: client creates a context
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* S1->S2: client submits execbuf with context
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* S2->S3: other clients submits execbuf with context
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* S3->S1: context object was retired
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* S3->S2: clients submits another execbuf
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* S2->S4: context destroy called with current context
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* S3->S5->S0: destroy path
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* S4->S5->S0: destroy path on current context
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*
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* There are two confusing terms used above:
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* The "current context" means the context which is currently running on the
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* GPU. The GPU has loaded its state already and has stored away the gtt
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* offset of the BO. The GPU is not actively referencing the data at this
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* offset, but it will on the next context switch. The only way to avoid this
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* is to do a GPU reset.
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*
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* An "active context' is one which was previously the "current context" and is
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* on the active list waiting for the next context switch to occur. Until this
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* happens, the object must remain at the same gtt offset. It is therefore
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* possible to destroy a context, but it is still active.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
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/* This is a HW constraint. The value below is the largest known requirement
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* I've seen in a spec to date, and that was a workaround for a non-shipping
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* part. It should be safe to decrease this, but it's more future proof as is.
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*/
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#define GEN6_CONTEXT_ALIGN (64<<10)
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#define GEN7_CONTEXT_ALIGN 4096
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static size_t get_context_alignment(struct drm_i915_private *dev_priv)
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{
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if (IS_GEN6(dev_priv))
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return GEN6_CONTEXT_ALIGN;
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return GEN7_CONTEXT_ALIGN;
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}
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static int get_context_size(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 reg;
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switch (INTEL_GEN(dev_priv)) {
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case 6:
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reg = I915_READ(CXT_SIZE);
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ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
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break;
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case 7:
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reg = I915_READ(GEN7_CXT_SIZE);
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if (IS_HASWELL(dev_priv))
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ret = HSW_CXT_TOTAL_SIZE;
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else
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ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
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break;
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case 8:
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ret = GEN8_CXT_TOTAL_SIZE;
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break;
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default:
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BUG();
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}
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return ret;
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}
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static void i915_gem_context_clean(struct i915_gem_context *ctx)
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{
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struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
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struct i915_vma *vma, *next;
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if (!ppgtt)
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return;
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list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
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vm_link) {
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if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
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break;
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}
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}
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void i915_gem_context_free(struct kref *ctx_ref)
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{
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struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
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int i;
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lockdep_assert_held(&ctx->i915->drm.struct_mutex);
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trace_i915_context_free(ctx);
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/*
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* This context is going away and we need to remove all VMAs still
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* around. This is to handle imported shared objects for which
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* destructor did not run when their handles were closed.
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*/
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i915_gem_context_clean(ctx);
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i915_ppgtt_put(ctx->ppgtt);
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for (i = 0; i < I915_NUM_ENGINES; i++) {
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struct intel_context *ce = &ctx->engine[i];
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if (!ce->state)
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continue;
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WARN_ON(ce->pin_count);
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if (ce->ringbuf)
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intel_ringbuffer_free(ce->ringbuf);
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drm_gem_object_unreference(&ce->state->base);
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}
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list_del(&ctx->link);
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ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
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kfree(ctx);
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}
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struct drm_i915_gem_object *
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i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
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{
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struct drm_i915_gem_object *obj;
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int ret;
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lockdep_assert_held(&dev->struct_mutex);
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obj = i915_gem_object_create(dev, size);
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if (IS_ERR(obj))
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return obj;
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/*
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* Try to make the context utilize L3 as well as LLC.
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*
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* On VLV we don't have L3 controls in the PTEs so we
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* shouldn't touch the cache level, especially as that
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* would make the object snooped which might have a
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* negative performance impact.
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*
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* Snooping is required on non-llc platforms in execlist
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* mode, but since all GGTT accesses use PAT entry 0 we
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* get snooping anyway regardless of cache_level.
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*
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* This is only applicable for Ivy Bridge devices since
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* later platforms don't have L3 control bits in the PTE.
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*/
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if (IS_IVYBRIDGE(dev)) {
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ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
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/* Failure shouldn't ever happen this early */
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if (WARN_ON(ret)) {
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drm_gem_object_unreference(&obj->base);
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return ERR_PTR(ret);
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}
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}
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return obj;
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}
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static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
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{
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int ret;
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ret = ida_simple_get(&dev_priv->context_hw_ida,
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0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
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if (ret < 0) {
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/* Contexts are only released when no longer active.
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* Flush any pending retires to hopefully release some
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* stale contexts and try again.
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*/
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i915_gem_retire_requests(dev_priv);
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ret = ida_simple_get(&dev_priv->context_hw_ida,
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0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
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if (ret < 0)
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return ret;
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}
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*out = ret;
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return 0;
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}
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static struct i915_gem_context *
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__create_hw_context(struct drm_device *dev,
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struct drm_i915_file_private *file_priv)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct i915_gem_context *ctx;
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int ret;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (ctx == NULL)
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return ERR_PTR(-ENOMEM);
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ret = assign_hw_id(dev_priv, &ctx->hw_id);
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if (ret) {
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kfree(ctx);
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return ERR_PTR(ret);
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}
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kref_init(&ctx->ref);
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list_add_tail(&ctx->link, &dev_priv->context_list);
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ctx->i915 = dev_priv;
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ctx->ggtt_alignment = get_context_alignment(dev_priv);
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if (dev_priv->hw_context_size) {
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struct drm_i915_gem_object *obj =
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i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
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if (IS_ERR(obj)) {
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ret = PTR_ERR(obj);
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goto err_out;
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}
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ctx->engine[RCS].state = obj;
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}
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/* Default context will never have a file_priv */
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if (file_priv != NULL) {
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ret = idr_alloc(&file_priv->context_idr, ctx,
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DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
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if (ret < 0)
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goto err_out;
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} else
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ret = DEFAULT_CONTEXT_HANDLE;
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ctx->file_priv = file_priv;
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ctx->user_handle = ret;
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/* NB: Mark all slices as needing a remap so that when the context first
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* loads it will restore whatever remap state already exists. If there
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* is no remap info, it will be a NOP. */
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ctx->remap_slice = ALL_L3_SLICES(dev_priv);
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ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
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ctx->ring_size = 4 * PAGE_SIZE;
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ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
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GEN8_CTX_ADDRESSING_MODE_SHIFT;
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ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
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return ctx;
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err_out:
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i915_gem_context_unreference(ctx);
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return ERR_PTR(ret);
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}
|
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|
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/**
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* The default context needs to exist per ring that uses contexts. It stores the
|
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* context state of the GPU for applications that don't utilize HW contexts, as
|
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* well as an idle case.
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*/
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static struct i915_gem_context *
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i915_gem_create_context(struct drm_device *dev,
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struct drm_i915_file_private *file_priv)
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{
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struct i915_gem_context *ctx;
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lockdep_assert_held(&dev->struct_mutex);
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ctx = __create_hw_context(dev, file_priv);
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if (IS_ERR(ctx))
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return ctx;
|
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|
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if (USES_FULL_PPGTT(dev)) {
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struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
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|
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if (IS_ERR(ppgtt)) {
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DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
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PTR_ERR(ppgtt));
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idr_remove(&file_priv->context_idr, ctx->user_handle);
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i915_gem_context_unreference(ctx);
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return ERR_CAST(ppgtt);
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}
|
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|
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ctx->ppgtt = ppgtt;
|
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}
|
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|
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trace_i915_context_create(ctx);
|
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|
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return ctx;
|
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}
|
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|
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/**
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* i915_gem_context_create_gvt - create a GVT GEM context
|
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* @dev: drm device *
|
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*
|
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* This function is used to create a GVT specific GEM context.
|
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*
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* Returns:
|
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* pointer to i915_gem_context on success, error pointer if failed
|
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*
|
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*/
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struct i915_gem_context *
|
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i915_gem_context_create_gvt(struct drm_device *dev)
|
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{
|
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struct i915_gem_context *ctx;
|
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int ret;
|
|
|
|
if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
|
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return ERR_PTR(-ENODEV);
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ERR_PTR(ret);
|
|
|
|
ctx = i915_gem_create_context(dev, NULL);
|
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if (IS_ERR(ctx))
|
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goto out;
|
|
|
|
ctx->execlists_force_single_submission = true;
|
|
ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
|
|
out:
|
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mutex_unlock(&dev->struct_mutex);
|
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return ctx;
|
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}
|
|
|
|
static void i915_gem_context_unpin(struct i915_gem_context *ctx,
|
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struct intel_engine_cs *engine)
|
|
{
|
|
if (i915.enable_execlists) {
|
|
intel_lr_context_unpin(ctx, engine);
|
|
} else {
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
|
|
|
if (ce->state)
|
|
i915_gem_object_ggtt_unpin(ce->state);
|
|
|
|
i915_gem_context_unreference(ctx);
|
|
}
|
|
}
|
|
|
|
void i915_gem_context_reset(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
lockdep_assert_held(&dev->struct_mutex);
|
|
|
|
if (i915.enable_execlists) {
|
|
struct i915_gem_context *ctx;
|
|
|
|
list_for_each_entry(ctx, &dev_priv->context_list, link)
|
|
intel_lr_context_reset(dev_priv, ctx);
|
|
}
|
|
|
|
i915_gem_context_lost(dev_priv);
|
|
}
|
|
|
|
int i915_gem_context_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct i915_gem_context *ctx;
|
|
|
|
/* Init should only be called once per module load. Eventually the
|
|
* restriction on the context_disabled check can be loosened. */
|
|
if (WARN_ON(dev_priv->kernel_context))
|
|
return 0;
|
|
|
|
if (intel_vgpu_active(dev_priv) &&
|
|
HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
|
|
if (!i915.enable_execlists) {
|
|
DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Using the simple ida interface, the max is limited by sizeof(int) */
|
|
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
|
|
ida_init(&dev_priv->context_hw_ida);
|
|
|
|
if (i915.enable_execlists) {
|
|
/* NB: intentionally left blank. We will allocate our own
|
|
* backing objects as we need them, thank you very much */
|
|
dev_priv->hw_context_size = 0;
|
|
} else if (HAS_HW_CONTEXTS(dev_priv)) {
|
|
dev_priv->hw_context_size =
|
|
round_up(get_context_size(dev_priv), 4096);
|
|
if (dev_priv->hw_context_size > (1<<20)) {
|
|
DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
|
|
dev_priv->hw_context_size);
|
|
dev_priv->hw_context_size = 0;
|
|
}
|
|
}
|
|
|
|
ctx = i915_gem_create_context(dev, NULL);
|
|
if (IS_ERR(ctx)) {
|
|
DRM_ERROR("Failed to create default global context (error %ld)\n",
|
|
PTR_ERR(ctx));
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
dev_priv->kernel_context = ctx;
|
|
|
|
DRM_DEBUG_DRIVER("%s context support initialized\n",
|
|
i915.enable_execlists ? "LR" :
|
|
dev_priv->hw_context_size ? "HW" : "fake");
|
|
return 0;
|
|
}
|
|
|
|
void i915_gem_context_lost(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
|
|
lockdep_assert_held(&dev_priv->drm.struct_mutex);
|
|
|
|
for_each_engine(engine, dev_priv) {
|
|
if (engine->last_context) {
|
|
i915_gem_context_unpin(engine->last_context, engine);
|
|
engine->last_context = NULL;
|
|
}
|
|
}
|
|
|
|
/* Force the GPU state to be restored on enabling */
|
|
if (!i915.enable_execlists) {
|
|
struct i915_gem_context *ctx;
|
|
|
|
list_for_each_entry(ctx, &dev_priv->context_list, link) {
|
|
if (!i915_gem_context_is_default(ctx))
|
|
continue;
|
|
|
|
for_each_engine(engine, dev_priv)
|
|
ctx->engine[engine->id].initialised = false;
|
|
|
|
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
|
|
}
|
|
|
|
for_each_engine(engine, dev_priv) {
|
|
struct intel_context *kce =
|
|
&dev_priv->kernel_context->engine[engine->id];
|
|
|
|
kce->initialised = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
void i915_gem_context_fini(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct i915_gem_context *dctx = dev_priv->kernel_context;
|
|
|
|
lockdep_assert_held(&dev->struct_mutex);
|
|
|
|
i915_gem_context_unreference(dctx);
|
|
dev_priv->kernel_context = NULL;
|
|
|
|
ida_destroy(&dev_priv->context_hw_ida);
|
|
}
|
|
|
|
static int context_idr_cleanup(int id, void *p, void *data)
|
|
{
|
|
struct i915_gem_context *ctx = p;
|
|
|
|
ctx->file_priv = ERR_PTR(-EBADF);
|
|
i915_gem_context_unreference(ctx);
|
|
return 0;
|
|
}
|
|
|
|
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct i915_gem_context *ctx;
|
|
|
|
idr_init(&file_priv->context_idr);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ctx = i915_gem_create_context(dev, file_priv);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (IS_ERR(ctx)) {
|
|
idr_destroy(&file_priv->context_idr);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
|
|
lockdep_assert_held(&dev->struct_mutex);
|
|
|
|
idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
|
|
idr_destroy(&file_priv->context_idr);
|
|
}
|
|
|
|
static inline int
|
|
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
|
|
{
|
|
struct drm_i915_private *dev_priv = req->i915;
|
|
struct intel_engine_cs *engine = req->engine;
|
|
u32 flags = hw_flags | MI_MM_SPACE_GTT;
|
|
const int num_rings =
|
|
/* Use an extended w/a on ivb+ if signalling from other rings */
|
|
i915_semaphore_is_enabled(dev_priv) ?
|
|
hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
|
|
0;
|
|
int len, ret;
|
|
|
|
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
|
|
* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
|
|
* explicitly, so we rely on the value at ring init, stored in
|
|
* itlb_before_ctx_switch.
|
|
*/
|
|
if (IS_GEN6(dev_priv)) {
|
|
ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* These flags are for resource streamer on HSW+ */
|
|
if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
|
|
flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
|
|
else if (INTEL_GEN(dev_priv) < 8)
|
|
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
|
|
|
|
|
|
len = 4;
|
|
if (INTEL_GEN(dev_priv) >= 7)
|
|
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
|
|
|
|
ret = intel_ring_begin(req, len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
|
|
if (INTEL_GEN(dev_priv) >= 7) {
|
|
intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
|
|
if (num_rings) {
|
|
struct intel_engine_cs *signaller;
|
|
|
|
intel_ring_emit(engine,
|
|
MI_LOAD_REGISTER_IMM(num_rings));
|
|
for_each_engine(signaller, dev_priv) {
|
|
if (signaller == engine)
|
|
continue;
|
|
|
|
intel_ring_emit_reg(engine,
|
|
RING_PSMI_CTL(signaller->mmio_base));
|
|
intel_ring_emit(engine,
|
|
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
|
|
}
|
|
}
|
|
}
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
intel_ring_emit(engine, MI_SET_CONTEXT);
|
|
intel_ring_emit(engine,
|
|
i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
|
|
flags);
|
|
/*
|
|
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
|
|
* WaMiSetContext_Hang:snb,ivb,vlv
|
|
*/
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
if (INTEL_GEN(dev_priv) >= 7) {
|
|
if (num_rings) {
|
|
struct intel_engine_cs *signaller;
|
|
i915_reg_t last_reg = {}; /* keep gcc quiet */
|
|
|
|
intel_ring_emit(engine,
|
|
MI_LOAD_REGISTER_IMM(num_rings));
|
|
for_each_engine(signaller, dev_priv) {
|
|
if (signaller == engine)
|
|
continue;
|
|
|
|
last_reg = RING_PSMI_CTL(signaller->mmio_base);
|
|
intel_ring_emit_reg(engine, last_reg);
|
|
intel_ring_emit(engine,
|
|
_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
|
|
}
|
|
|
|
/* Insert a delay before the next switch! */
|
|
intel_ring_emit(engine,
|
|
MI_STORE_REGISTER_MEM |
|
|
MI_SRM_LRM_GLOBAL_GTT);
|
|
intel_ring_emit_reg(engine, last_reg);
|
|
intel_ring_emit(engine, engine->scratch.gtt_offset);
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
}
|
|
intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE);
|
|
}
|
|
|
|
intel_ring_advance(engine);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int remap_l3(struct drm_i915_gem_request *req, int slice)
|
|
{
|
|
u32 *remap_info = req->i915->l3_parity.remap_info[slice];
|
|
struct intel_engine_cs *engine = req->engine;
|
|
int i, ret;
|
|
|
|
if (!remap_info)
|
|
return 0;
|
|
|
|
ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Note: We do not worry about the concurrent register cacheline hang
|
|
* here because no other code should access these registers other than
|
|
* at initialization time.
|
|
*/
|
|
intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
|
|
for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
|
|
intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
|
|
intel_ring_emit(engine, remap_info[i]);
|
|
}
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
intel_ring_advance(engine);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
|
|
struct intel_engine_cs *engine,
|
|
struct i915_gem_context *to)
|
|
{
|
|
if (to->remap_slice)
|
|
return false;
|
|
|
|
if (!to->engine[RCS].initialised)
|
|
return false;
|
|
|
|
if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
|
|
return false;
|
|
|
|
return to == engine->last_context;
|
|
}
|
|
|
|
static bool
|
|
needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
|
|
struct intel_engine_cs *engine,
|
|
struct i915_gem_context *to)
|
|
{
|
|
if (!ppgtt)
|
|
return false;
|
|
|
|
/* Always load the ppgtt on first use */
|
|
if (!engine->last_context)
|
|
return true;
|
|
|
|
/* Same context without new entries, skip */
|
|
if (engine->last_context == to &&
|
|
!(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
|
|
return false;
|
|
|
|
if (engine->id != RCS)
|
|
return true;
|
|
|
|
if (INTEL_GEN(engine->i915) < 8)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool
|
|
needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
|
|
struct i915_gem_context *to,
|
|
u32 hw_flags)
|
|
{
|
|
if (!ppgtt)
|
|
return false;
|
|
|
|
if (!IS_GEN8(to->i915))
|
|
return false;
|
|
|
|
if (hw_flags & MI_RESTORE_INHIBIT)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int do_rcs_switch(struct drm_i915_gem_request *req)
|
|
{
|
|
struct i915_gem_context *to = req->ctx;
|
|
struct intel_engine_cs *engine = req->engine;
|
|
struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
|
|
struct i915_gem_context *from;
|
|
u32 hw_flags;
|
|
int ret, i;
|
|
|
|
if (skip_rcs_switch(ppgtt, engine, to))
|
|
return 0;
|
|
|
|
/* Trying to pin first makes error handling easier. */
|
|
ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
|
|
to->ggtt_alignment,
|
|
0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Pin can switch back to the default context if we end up calling into
|
|
* evict_everything - as a last ditch gtt defrag effort that also
|
|
* switches to the default context. Hence we need to reload from here.
|
|
*
|
|
* XXX: Doing so is painfully broken!
|
|
*/
|
|
from = engine->last_context;
|
|
|
|
/*
|
|
* Clear this page out of any CPU caches for coherent swap-in/out. Note
|
|
* that thanks to write = false in this call and us not setting any gpu
|
|
* write domains when putting a context object onto the active list
|
|
* (when switching away from it), this won't block.
|
|
*
|
|
* XXX: We need a real interface to do this instead of trickery.
|
|
*/
|
|
ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false);
|
|
if (ret)
|
|
goto unpin_out;
|
|
|
|
if (needs_pd_load_pre(ppgtt, engine, to)) {
|
|
/* Older GENs and non render rings still want the load first,
|
|
* "PP_DCLV followed by PP_DIR_BASE register through Load
|
|
* Register Immediate commands in Ring Buffer before submitting
|
|
* a context."*/
|
|
trace_switch_mm(engine, to);
|
|
ret = ppgtt->switch_mm(ppgtt, req);
|
|
if (ret)
|
|
goto unpin_out;
|
|
}
|
|
|
|
if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
|
|
/* NB: If we inhibit the restore, the context is not allowed to
|
|
* die because future work may end up depending on valid address
|
|
* space. This means we must enforce that a page table load
|
|
* occur when this occurs. */
|
|
hw_flags = MI_RESTORE_INHIBIT;
|
|
else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
|
|
hw_flags = MI_FORCE_RESTORE;
|
|
else
|
|
hw_flags = 0;
|
|
|
|
if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
|
|
ret = mi_set_context(req, hw_flags);
|
|
if (ret)
|
|
goto unpin_out;
|
|
}
|
|
|
|
/* The backing object for the context is done after switching to the
|
|
* *next* context. Therefore we cannot retire the previous context until
|
|
* the next context has already started running. In fact, the below code
|
|
* is a bit suboptimal because the retiring can occur simply after the
|
|
* MI_SET_CONTEXT instead of when the next seqno has completed.
|
|
*/
|
|
if (from != NULL) {
|
|
from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
|
|
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
|
|
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
|
|
* whole damn pipeline, we don't need to explicitly mark the
|
|
* object dirty. The only exception is that the context must be
|
|
* correct in case the object gets swapped out. Ideally we'd be
|
|
* able to defer doing this until we know the object would be
|
|
* swapped, but there is no way to do that yet.
|
|
*/
|
|
from->engine[RCS].state->dirty = 1;
|
|
|
|
/* obj is kept alive until the next request by its active ref */
|
|
i915_gem_object_ggtt_unpin(from->engine[RCS].state);
|
|
i915_gem_context_unreference(from);
|
|
}
|
|
i915_gem_context_reference(to);
|
|
engine->last_context = to;
|
|
|
|
/* GEN8 does *not* require an explicit reload if the PDPs have been
|
|
* setup, and we do not wish to move them.
|
|
*/
|
|
if (needs_pd_load_post(ppgtt, to, hw_flags)) {
|
|
trace_switch_mm(engine, to);
|
|
ret = ppgtt->switch_mm(ppgtt, req);
|
|
/* The hardware context switch is emitted, but we haven't
|
|
* actually changed the state - so it's probably safe to bail
|
|
* here. Still, let the user know something dangerous has
|
|
* happened.
|
|
*/
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (ppgtt)
|
|
ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
|
|
|
|
for (i = 0; i < MAX_L3_SLICES; i++) {
|
|
if (!(to->remap_slice & (1<<i)))
|
|
continue;
|
|
|
|
ret = remap_l3(req, i);
|
|
if (ret)
|
|
return ret;
|
|
|
|
to->remap_slice &= ~(1<<i);
|
|
}
|
|
|
|
if (!to->engine[RCS].initialised) {
|
|
if (engine->init_context) {
|
|
ret = engine->init_context(req);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
to->engine[RCS].initialised = true;
|
|
}
|
|
|
|
return 0;
|
|
|
|
unpin_out:
|
|
i915_gem_object_ggtt_unpin(to->engine[RCS].state);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* i915_switch_context() - perform a GPU context switch.
|
|
* @req: request for which we'll execute the context switch
|
|
*
|
|
* The context life cycle is simple. The context refcount is incremented and
|
|
* decremented by 1 and create and destroy. If the context is in use by the GPU,
|
|
* it will have a refcount > 1. This allows us to destroy the context abstract
|
|
* object while letting the normal object tracking destroy the backing BO.
|
|
*
|
|
* This function should not be used in execlists mode. Instead the context is
|
|
* switched by writing to the ELSP and requests keep a reference to their
|
|
* context.
|
|
*/
|
|
int i915_switch_context(struct drm_i915_gem_request *req)
|
|
{
|
|
struct intel_engine_cs *engine = req->engine;
|
|
|
|
WARN_ON(i915.enable_execlists);
|
|
lockdep_assert_held(&req->i915->drm.struct_mutex);
|
|
|
|
if (!req->ctx->engine[engine->id].state) {
|
|
struct i915_gem_context *to = req->ctx;
|
|
struct i915_hw_ppgtt *ppgtt =
|
|
to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
|
|
|
|
if (needs_pd_load_pre(ppgtt, engine, to)) {
|
|
int ret;
|
|
|
|
trace_switch_mm(engine, to);
|
|
ret = ppgtt->switch_mm(ppgtt, req);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
|
|
}
|
|
|
|
if (to != engine->last_context) {
|
|
i915_gem_context_reference(to);
|
|
if (engine->last_context)
|
|
i915_gem_context_unreference(engine->last_context);
|
|
engine->last_context = to;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
return do_rcs_switch(req);
|
|
}
|
|
|
|
static bool contexts_enabled(struct drm_device *dev)
|
|
{
|
|
return i915.enable_execlists || to_i915(dev)->hw_context_size;
|
|
}
|
|
|
|
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_gem_context_create *args = data;
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct i915_gem_context *ctx;
|
|
int ret;
|
|
|
|
if (!contexts_enabled(dev))
|
|
return -ENODEV;
|
|
|
|
if (args->pad != 0)
|
|
return -EINVAL;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_create_context(dev, file_priv);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (IS_ERR(ctx))
|
|
return PTR_ERR(ctx);
|
|
|
|
args->ctx_id = ctx->user_handle;
|
|
DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_gem_context_destroy *args = data;
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct i915_gem_context *ctx;
|
|
int ret;
|
|
|
|
if (args->pad != 0)
|
|
return -EINVAL;
|
|
|
|
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
|
|
return -ENOENT;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
|
|
if (IS_ERR(ctx)) {
|
|
mutex_unlock(&dev->struct_mutex);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
idr_remove(&file_priv->context_idr, ctx->user_handle);
|
|
i915_gem_context_unreference(ctx);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
|
|
return 0;
|
|
}
|
|
|
|
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct drm_i915_gem_context_param *args = data;
|
|
struct i915_gem_context *ctx;
|
|
int ret;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
|
|
if (IS_ERR(ctx)) {
|
|
mutex_unlock(&dev->struct_mutex);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
args->size = 0;
|
|
switch (args->param) {
|
|
case I915_CONTEXT_PARAM_BAN_PERIOD:
|
|
args->value = ctx->hang_stats.ban_period_seconds;
|
|
break;
|
|
case I915_CONTEXT_PARAM_NO_ZEROMAP:
|
|
args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
|
|
break;
|
|
case I915_CONTEXT_PARAM_GTT_SIZE:
|
|
if (ctx->ppgtt)
|
|
args->value = ctx->ppgtt->base.total;
|
|
else if (to_i915(dev)->mm.aliasing_ppgtt)
|
|
args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
|
|
else
|
|
args->value = to_i915(dev)->ggtt.base.total;
|
|
break;
|
|
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
|
|
args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct drm_i915_gem_context_param *args = data;
|
|
struct i915_gem_context *ctx;
|
|
int ret;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
|
|
if (IS_ERR(ctx)) {
|
|
mutex_unlock(&dev->struct_mutex);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
switch (args->param) {
|
|
case I915_CONTEXT_PARAM_BAN_PERIOD:
|
|
if (args->size)
|
|
ret = -EINVAL;
|
|
else if (args->value < ctx->hang_stats.ban_period_seconds &&
|
|
!capable(CAP_SYS_ADMIN))
|
|
ret = -EPERM;
|
|
else
|
|
ctx->hang_stats.ban_period_seconds = args->value;
|
|
break;
|
|
case I915_CONTEXT_PARAM_NO_ZEROMAP:
|
|
if (args->size) {
|
|
ret = -EINVAL;
|
|
} else {
|
|
ctx->flags &= ~CONTEXT_NO_ZEROMAP;
|
|
ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
|
|
}
|
|
break;
|
|
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
|
|
if (args->size) {
|
|
ret = -EINVAL;
|
|
} else {
|
|
if (args->value)
|
|
ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
|
|
else
|
|
ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
|
|
}
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
|
|
void *data, struct drm_file *file)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct drm_i915_reset_stats *args = data;
|
|
struct i915_ctx_hang_stats *hs;
|
|
struct i915_gem_context *ctx;
|
|
int ret;
|
|
|
|
if (args->flags || args->pad)
|
|
return -EINVAL;
|
|
|
|
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
|
|
return -EPERM;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
|
|
if (IS_ERR(ctx)) {
|
|
mutex_unlock(&dev->struct_mutex);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
hs = &ctx->hang_stats;
|
|
|
|
if (capable(CAP_SYS_ADMIN))
|
|
args->reset_count = i915_reset_count(&dev_priv->gpu_error);
|
|
else
|
|
args->reset_count = 0;
|
|
|
|
args->batch_active = hs->batch_active;
|
|
args->batch_pending = hs->batch_pending;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return 0;
|
|
}
|