AuxXxilium/linux_dsm_epyc7002
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bebbc4bcf3
linux_dsm_epyc7002/arch/xtensa/boot/dts
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Scott Telford bebbc4bcf3 xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config. 
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-19 11:51:32 -07:00
..
csp.dts xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config. 2016-09-19 11:51:32 -07:00
kc705_nommu.dts xtensa: nommu: xtfpga: add kc705 DTS 2015-11-02 18:03:11 +03:00
kc705.dts xtensa: xtfpga: fix earlycon endianness 2016-03-11 08:53:32 +00:00
lx60.dts xtensa: standardize devicetree cpu compatible strings 2014-01-15 00:21:25 +04:00
lx200mx.dts xtensa: xtfpga: add lx200 SMP DTS and defconfig 2014-10-21 13:28:43 +04:00
Makefile xtensa: enable building of all dtbs 2015-10-27 16:12:16 -05:00
ml605.dts xtensa: standardize devicetree cpu compatible strings 2014-01-15 00:21:25 +04:00
xtfpga-flash-4m.dtsi xtensa: xtfpga: introduce SoC I/O bus 2014-04-06 21:32:02 +04:00
xtfpga-flash-16m.dtsi xtensa: xtfpga: introduce SoC I/O bus 2014-04-06 21:32:02 +04:00
xtfpga-flash-128m.dtsi xtensa: add support for KC705 2014-04-06 21:32:02 +04:00
xtfpga.dtsi xtensa: xtfpga: fix earlycon endianness 2016-03-11 08:53:32 +00:00