mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
8a8005e3e1
Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
572 lines
12 KiB
C
572 lines
12 KiB
C
/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/workqueue.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include "dpaux.h"
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#include "drm.h"
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static DEFINE_MUTEX(dpaux_lock);
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static LIST_HEAD(dpaux_list);
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struct tegra_dpaux {
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struct drm_dp_aux aux;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct tegra_output *output;
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk;
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struct regulator *vdd;
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struct completion complete;
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struct work_struct work;
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struct list_head list;
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};
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static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
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{
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return container_of(aux, struct tegra_dpaux, aux);
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}
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static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
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{
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return container_of(work, struct tegra_dpaux, work);
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}
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static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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unsigned long offset)
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{
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return readl(dpaux->regs + (offset << 2));
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}
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static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
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u32 value, unsigned long offset)
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{
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writel(value, dpaux->regs + (offset << 2));
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}
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static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
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size_t size)
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{
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size_t i, j;
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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u32 value = 0;
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for (j = 0; j < num; j++)
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value |= buffer[i * 4 + j] << (j * 8);
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
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}
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}
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static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
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size_t size)
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{
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size_t i, j;
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
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for (j = 0; j < num; j++)
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buffer[i * 4 + j] = value >> (j * 8);
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}
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}
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static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
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struct drm_dp_aux_msg *msg)
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{
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unsigned long timeout = msecs_to_jiffies(250);
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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unsigned long status;
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ssize_t ret = 0;
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u32 value;
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/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
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if (msg->size > 16)
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return -EINVAL;
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/*
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* Allow zero-sized messages only for I2C, in which case they specify
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* address-only transactions.
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*/
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if (msg->size < 1) {
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_READ:
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value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
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break;
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default:
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return -EINVAL;
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}
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} else {
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/* For non-zero-sized messages, set the CMDLEN field. */
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value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
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}
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
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break;
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case DP_AUX_I2C_READ:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
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break;
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case DP_AUX_I2C_STATUS:
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if (msg->request & DP_AUX_I2C_MOT)
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
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else
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
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break;
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case DP_AUX_NATIVE_WRITE:
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value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
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break;
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case DP_AUX_NATIVE_READ:
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value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
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break;
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default:
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return -EINVAL;
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}
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tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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if ((msg->request & DP_AUX_I2C_READ) == 0) {
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tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
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ret = msg->size;
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}
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/* start transaction */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
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value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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status = wait_for_completion_timeout(&dpaux->complete, timeout);
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if (!status)
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return -ETIMEDOUT;
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/* read status and clear errors */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
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return -ETIMEDOUT;
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if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
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return -EIO;
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switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
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case 0x00:
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msg->reply = DP_AUX_NATIVE_REPLY_ACK;
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break;
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case 0x01:
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msg->reply = DP_AUX_NATIVE_REPLY_NACK;
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break;
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case 0x02:
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msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
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break;
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case 0x04:
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msg->reply = DP_AUX_I2C_REPLY_NACK;
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break;
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case 0x08:
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msg->reply = DP_AUX_I2C_REPLY_DEFER;
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break;
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}
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if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
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if (msg->request & DP_AUX_I2C_READ) {
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size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
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if (WARN_ON(count != msg->size))
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count = min_t(size_t, count, msg->size);
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tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
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ret = count;
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}
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}
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return ret;
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}
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static void tegra_dpaux_hotplug(struct work_struct *work)
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{
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struct tegra_dpaux *dpaux = work_to_dpaux(work);
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if (dpaux->output)
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drm_helper_hpd_irq_event(dpaux->output->connector.dev);
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}
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static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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{
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struct tegra_dpaux *dpaux = data;
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irqreturn_t ret = IRQ_HANDLED;
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u32 value;
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/* clear interrupts */
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value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
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schedule_work(&dpaux->work);
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if (value & DPAUX_INTR_IRQ_EVENT) {
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/* TODO: handle this */
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}
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if (value & DPAUX_INTR_AUX_DONE)
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complete(&dpaux->complete);
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return ret;
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}
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static int tegra_dpaux_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux;
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struct resource *regs;
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u32 value;
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int err;
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dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
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if (!dpaux)
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return -ENOMEM;
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INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
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init_completion(&dpaux->complete);
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INIT_LIST_HEAD(&dpaux->list);
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dpaux->dev = &pdev->dev;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(dpaux->regs))
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return PTR_ERR(dpaux->regs);
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dpaux->irq = platform_get_irq(pdev, 0);
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if (dpaux->irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ\n");
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return -ENXIO;
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}
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dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
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if (IS_ERR(dpaux->rst))
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return PTR_ERR(dpaux->rst);
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dpaux->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dpaux->clk))
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return PTR_ERR(dpaux->clk);
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err = clk_prepare_enable(dpaux->clk);
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if (err < 0)
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return err;
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reset_control_deassert(dpaux->rst);
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dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
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if (IS_ERR(dpaux->clk_parent))
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return PTR_ERR(dpaux->clk_parent);
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err = clk_prepare_enable(dpaux->clk_parent);
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if (err < 0)
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return err;
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err = clk_set_rate(dpaux->clk_parent, 270000000);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
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err);
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return err;
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}
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dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(dpaux->vdd))
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return PTR_ERR(dpaux->vdd);
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err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
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dev_name(dpaux->dev), dpaux);
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if (err < 0) {
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dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
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dpaux->irq, err);
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return err;
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}
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dpaux->aux.transfer = tegra_dpaux_transfer;
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dpaux->aux.dev = &pdev->dev;
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err = drm_dp_aux_register(&dpaux->aux);
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if (err < 0)
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return err;
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/* enable and clear all interrupts */
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value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
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DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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mutex_lock(&dpaux_lock);
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list_add_tail(&dpaux->list, &dpaux_list);
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mutex_unlock(&dpaux_lock);
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platform_set_drvdata(pdev, dpaux);
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return 0;
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}
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static int tegra_dpaux_remove(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
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drm_dp_aux_unregister(&dpaux->aux);
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mutex_lock(&dpaux_lock);
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list_del(&dpaux->list);
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mutex_unlock(&dpaux_lock);
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cancel_work_sync(&dpaux->work);
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clk_disable_unprepare(dpaux->clk_parent);
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reset_control_assert(dpaux->rst);
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clk_disable_unprepare(dpaux->clk);
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return 0;
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}
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static const struct of_device_id tegra_dpaux_of_match[] = {
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{ .compatible = "nvidia,tegra124-dpaux", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
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struct platform_driver tegra_dpaux_driver = {
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.driver = {
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.name = "tegra-dpaux",
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.of_match_table = tegra_dpaux_of_match,
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},
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.probe = tegra_dpaux_probe,
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.remove = tegra_dpaux_remove,
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};
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struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
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{
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struct tegra_dpaux *dpaux;
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mutex_lock(&dpaux_lock);
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list_for_each_entry(dpaux, &dpaux_list, list)
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if (np == dpaux->dev->of_node) {
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mutex_unlock(&dpaux_lock);
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return dpaux;
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}
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mutex_unlock(&dpaux_lock);
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return NULL;
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}
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int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
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{
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unsigned long timeout;
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int err;
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output->connector.polled = DRM_CONNECTOR_POLL_HPD;
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dpaux->output = output;
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err = regulator_enable(dpaux->vdd);
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if (err < 0)
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return err;
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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enum drm_connector_status status;
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status = tegra_dpaux_detect(dpaux);
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if (status == connector_status_connected)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
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{
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unsigned long timeout;
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int err;
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err = regulator_disable(dpaux->vdd);
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if (err < 0)
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return err;
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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enum drm_connector_status status;
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status = tegra_dpaux_detect(dpaux);
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if (status == connector_status_disconnected) {
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dpaux->output = NULL;
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return 0;
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}
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
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{
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
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return connector_status_connected;
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return connector_status_disconnected;
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}
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int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
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{
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u32 value;
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value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
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DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
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DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
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DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
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DPAUX_HYBRID_PADCTL_MODE_AUX;
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tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
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value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
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tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
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return 0;
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}
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int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
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{
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
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tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
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return 0;
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}
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int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
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{
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int err;
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err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
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encoding);
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if (err < 0)
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return err;
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return 0;
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}
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int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
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u8 pattern)
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{
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u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
|
|
u8 status[DP_LINK_STATUS_SIZE], values[4];
|
|
unsigned int i;
|
|
int err;
|
|
|
|
err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
if (tp == DP_TRAINING_PATTERN_DISABLE)
|
|
return 0;
|
|
|
|
for (i = 0; i < link->num_lanes; i++)
|
|
values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
|
|
DP_TRAIN_PRE_EMPH_LEVEL_0 |
|
|
DP_TRAIN_MAX_SWING_REACHED |
|
|
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
|
|
|
|
err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
|
|
link->num_lanes);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
usleep_range(500, 1000);
|
|
|
|
err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
switch (tp) {
|
|
case DP_TRAINING_PATTERN_1:
|
|
if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
|
|
return -EAGAIN;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
if (!drm_dp_channel_eq_ok(status, link->num_lanes))
|
|
return -EAGAIN;
|
|
|
|
break;
|
|
|
|
default:
|
|
dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|