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ff050ad12c
Lots of changes specific to one of the SoC families. Some that stick out are: * mach-qcom gains new features, most importantly SMP support for the newer chips (Stephen Boyd, Rohit Vaswani) * mvebu gains support for three new SoCs: Armada 375, 380 and 385 (Thomas Petazzoni and Free-electrons team) * SMP support for Rockchips (Heiko Stübner) * Lots of i.MX changes (Shawn Guo) * Added support for BCM5301x SoC (Hauke Mehrtens) * Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn and Sebastian Hesselbarth doing the final part of a long journey) * Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd Bergmann) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/yT2CrR//JCVInAQJN8A/9Ft1rfp4LEe8Lpr9yAZydG4UaJKy8Hh7Z fmohMAuy88J+8jzdwQKKCeEiId+nIf+WmFIQDn9YRDev1/T2v32Ax49XuGtY47JX 4loIC2wR0+j1aSwhEVOmlM03lX7Hbu6iNDkxaLkDKTRrt3DhDNA6cPZYwNOT273W Yx7hIDpvsoOVN3zbPwqhwLrXgywsaNB9E7ly1GixRd1thdg46kMRcM0LJSXPH3we pyx7sZbILTVMeUx79XUTvBDJYsbjJWFZknVDYXGkrS5YxAASVsVW2KW9fP9E+UXE wTmOxg6spsHGgCezwy8NL5UmfaAOXL3mm6ginFwWpyz7Iu+P5IvfR1W+8UA/O8tp K9y8wLA64chPQJkAGaPQBqUPq9QkNHodZWgaPKxKuuv3qF481DCnQKkFRz+sl7mu oQVGnoMCnTY6L6yYcIq/GpgiJ731vwefirAwPR8FEBN/gw/gC01b+DDchx/5inPJ 6V6dCEtPZxXMOsIaYBWFauk3pMFU3E8coklmteyYDQg7eb+55Zq3vsNEpu/vb6ll M660AQzzbkZ7lgsSBdNODEvkNH15kC35G2UCfwy99uCE4k/0Vi7reJ1BzXkc+dtJ +maBtA6NMALXQ/EI+B+fZLccI4Hv7avwFy1rQJaf+TLiFvTd9yp0qUX8JjXWDPgu pPWQOC4a9mU= =AGpV -----END PGP SIGNATURE----- Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC specific changes from Arnd Bergmann: "Lots of changes specific to one of the SoC families. Some that stick out are: - mach-qcom gains new features, most importantly SMP support for the newer chips (Stephen Boyd, Rohit Vaswani) - mvebu gains support for three new SoCs: Armada 375, 380 and 385 (Thomas Petazzoni and Free-electrons team) - SMP support for Rockchips (Heiko Stübner) - Lots of i.MX changes (Shawn Guo) - Added support for BCM5301x SoC (Hauke Mehrtens) - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn and Sebastian Hesselbarth doing the final part of a long journey) - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd Bergmann)" * tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits) ARM: sunxi: Select HAVE_ARM_ARCH_TIMER ARM: cache-tauros2: remove ARMv6 code ARM: mvebu: don't select CONFIG_NEON ARM: davinci: fix DT booting with default defconfig ARM: configs: bcm_defconfig: enable bcm590xx regulator support ARM: davinci: remove tnetv107x support MAINTAINERS: Update ARM STi maintainers ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE ARM: bcm21664: Add board support. ARM: sunxi: Add the new watchog compatibles to the reboot code ARM: enable ARM_HAS_SG_CHAIN for multiplatform ARM: davinci: remove da8xx_omapl_defconfig ARM: davinci: da8xx: fix multiple watchdog device registration ARM: davinci: add da8xx specific configs to davinci_all_defconfig ARM: davinci: enable da8xx build concurrently with older devices ARM: BCM5301X: workaround suppress fault ARM: BCM5301X: add early debugging support ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU ARM: mach-bcm: Remove GENERIC_TIME ARM: shmobile: APMU: Fix warnings due to improper printk formats ...
197 lines
5.8 KiB
C
197 lines
5.8 KiB
C
/*
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* OMAP4 PRM instance functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "iomap.h"
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#include "common.h"
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#include "prcm-common.h"
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#include "prm44xx.h"
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#include "prm54xx.h"
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#include "prm7xx.h"
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#include "prminst44xx.h"
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#include "prm-regbits-44xx.h"
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#include "prcm44xx.h"
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#include "prcm43xx.h"
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#include "prcm_mpu44xx.h"
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#include "soc.h"
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static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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/**
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* omap_prm_base_init - Populates the prm partitions
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*
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* Populates the base addresses of the _prm_bases
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* array used for read/write of prm module registers.
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*/
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void omap_prm_base_init(void)
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{
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_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
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_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
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}
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/* Read a register in a PRM instance */
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u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_prm_bases[part]);
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return __raw_readl(_prm_bases[part] + inst + idx);
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}
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/* Write into a register in a PRM instance */
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void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_prm_bases[part]);
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__raw_writel(val, _prm_bases[part] + inst + idx);
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}
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/* Read-modify-write a register in PRM. Caller must lock */
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u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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u16 idx)
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{
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u32 v;
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v = omap4_prminst_read_inst_reg(part, inst, idx);
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v &= ~mask;
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v |= bits;
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omap4_prminst_write_inst_reg(v, part, inst, idx);
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return v;
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}
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to check
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL upon parameter error.
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*/
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int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 v;
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v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
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v &= 1 << shift;
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v >>= shift;
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return v;
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}
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/**
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* omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to assert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 mask = 1 << shift;
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omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
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return 0;
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}
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/**
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* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to deassert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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int c;
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u32 mask = 1 << shift;
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u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstctrl_offs) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
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rstst_offs);
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/* de-assert the reset control line */
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omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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void omap4_prminst_global_warm_sw_reset(void)
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{
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u32 v;
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s16 dev_inst;
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if (cpu_is_omap44xx())
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dev_inst = OMAP4430_PRM_DEVICE_INST;
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else if (soc_is_omap54xx())
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dev_inst = OMAP54XX_PRM_DEVICE_INST;
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else if (soc_is_dra7xx())
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dev_inst = DRA7XX_PRM_DEVICE_INST;
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else if (soc_is_am43xx())
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dev_inst = AM43XX_PRM_DEVICE_INST;
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else
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return;
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v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
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omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
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dev_inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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/* OCP barrier */
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v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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dev_inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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}
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