mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 20:26:40 +07:00
382414b93a
This change adds support for the sh7372 A4R power domain. The sh7372 A4R hardware power domain contains the SH CPU Core and a set of I/O devices including multimedia accelerators and I2C controllers. One special case about A4R is the INTCS interrupt controller that needs to be saved and restored to keep working as expected. Also the LCDC hardware blocks are in a different hardware power domain but have their IRQs routed only through INTCS. So as long as LCDCs are active we cannot power down INTCS because that would risk losing interrupts. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
1038 lines
23 KiB
C
1038 lines
23 KiB
C
/*
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* sh7372 processor support
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/uio_driver.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_intc.h>
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#include <linux/sh_timer.h>
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#include <linux/pm_domain.h>
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#include <mach/hardware.h>
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#include <mach/sh7372.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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/* SCIFA0 */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xe6c40000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
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evt2irq(0x0c00), evt2irq(0x0c00) },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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/* SCIFA1 */
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xe6c50000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
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evt2irq(0x0c20), evt2irq(0x0c20) },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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/* SCIFA2 */
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xe6c60000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
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evt2irq(0x0c40), evt2irq(0x0c40) },
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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/* SCIFA3 */
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xe6c70000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
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evt2irq(0x0c60), evt2irq(0x0c60) },
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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/* SCIFA4 */
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xe6c80000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
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evt2irq(0x0d20), evt2irq(0x0d20) },
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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/* SCIFA5 */
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xe6cb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
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evt2irq(0x0d40), evt2irq(0x0d40) },
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};
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static struct platform_device scif5_device = {
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.name = "sh-sci",
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.id = 5,
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.dev = {
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.platform_data = &scif5_platform_data,
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},
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};
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/* SCIFB */
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static struct plat_sci_port scif6_platform_data = {
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.mapbase = 0xe6c30000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFB,
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.irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
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evt2irq(0x0d60), evt2irq(0x0d60) },
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};
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static struct platform_device scif6_device = {
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.name = "sh-sci",
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.id = 6,
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.dev = {
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.platform_data = &scif6_platform_data,
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},
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};
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/* CMT */
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static struct sh_timer_config cmt2_platform_data = {
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.name = "CMT2",
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.channel_offset = 0x40,
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.timer_bit = 5,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt2_resources[] = {
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[0] = {
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.name = "CMT2",
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.start = 0xe6130040,
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.end = 0xe613004b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x0b80), /* CMT2 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt2_device = {
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.name = "sh_cmt",
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.id = 2,
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.dev = {
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.platform_data = &cmt2_platform_data,
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},
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.resource = cmt2_resources,
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.num_resources = ARRAY_SIZE(cmt2_resources),
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};
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/* TMU */
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static struct sh_timer_config tmu00_platform_data = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource tmu00_resources[] = {
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[0] = {
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.name = "TMU00",
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.start = 0xfff60008,
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.end = 0xfff60013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu00_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu00_platform_data,
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},
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.resource = tmu00_resources,
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.num_resources = ARRAY_SIZE(tmu00_resources),
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};
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static struct sh_timer_config tmu01_platform_data = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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static struct resource tmu01_resources[] = {
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[0] = {
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.name = "TMU01",
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.start = 0xfff60014,
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.end = 0xfff6001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu01_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu01_platform_data,
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},
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.resource = tmu01_resources,
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.num_resources = ARRAY_SIZE(tmu01_resources),
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};
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/* I2C */
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static struct resource iic0_resources[] = {
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[0] = {
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.name = "IIC0",
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.start = 0xFFF20000,
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.end = 0xFFF20425 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
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.end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device iic0_device = {
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.name = "i2c-sh_mobile",
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.id = 0, /* "i2c0" clock */
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.num_resources = ARRAY_SIZE(iic0_resources),
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.resource = iic0_resources,
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};
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static struct resource iic1_resources[] = {
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[0] = {
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.name = "IIC1",
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.start = 0xE6C20000,
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.end = 0xE6C20425 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x780), /* IIC1_ALI1 */
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.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device iic1_device = {
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.name = "i2c-sh_mobile",
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.id = 1, /* "i2c1" clock */
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.num_resources = ARRAY_SIZE(iic1_resources),
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.resource = iic1_resources,
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};
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/* DMA */
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_512BIT = 5,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_128BIT] = 4, \
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[XMIT_SZ_256BIT] = 5, \
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[XMIT_SZ_512BIT] = 6, \
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}
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#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
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(((i) & 0xc) << (20 - 2)))
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static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SCIF0_TX,
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.addr = 0xe6c40020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF0_RX,
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.addr = 0xe6c40024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_TX,
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.addr = 0xe6c50020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x25,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_RX,
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.addr = 0xe6c50024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x26,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_TX,
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.addr = 0xe6c60020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_RX,
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.addr = 0xe6c60024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_TX,
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.addr = 0xe6c70020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_RX,
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.addr = 0xe6c70024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2e,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_TX,
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.addr = 0xe6c80020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x39,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_RX,
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.addr = 0xe6c80024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x3a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_TX,
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.addr = 0xe6cb0020,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x35,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_RX,
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.addr = 0xe6cb0024,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x36,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_TX,
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.addr = 0xe6c30040,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x3d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_RX,
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.addr = 0xe6c30060,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x3e,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_TX,
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.addr = 0xe6850030,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xc1,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_RX,
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.addr = 0xe6850030,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xc2,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_TX,
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.addr = 0xe6860030,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xc9,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_RX,
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.addr = 0xe6860030,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xca,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_TX,
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.addr = 0xe6870030,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xcd,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_RX,
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.addr = 0xe6870030,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
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.mid_rid = 0xce,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_TX,
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.addr = 0xe6bd0034,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xd1,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_RX,
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.addr = 0xe6bd0034,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
|
|
.mid_rid = 0xd2,
|
|
},
|
|
};
|
|
|
|
static const struct sh_dmae_channel sh7372_dmae_channels[] = {
|
|
{
|
|
.offset = 0,
|
|
.dmars = 0,
|
|
.dmars_bit = 0,
|
|
}, {
|
|
.offset = 0x10,
|
|
.dmars = 0,
|
|
.dmars_bit = 8,
|
|
}, {
|
|
.offset = 0x20,
|
|
.dmars = 4,
|
|
.dmars_bit = 0,
|
|
}, {
|
|
.offset = 0x30,
|
|
.dmars = 4,
|
|
.dmars_bit = 8,
|
|
}, {
|
|
.offset = 0x50,
|
|
.dmars = 8,
|
|
.dmars_bit = 0,
|
|
}, {
|
|
.offset = 0x60,
|
|
.dmars = 8,
|
|
.dmars_bit = 8,
|
|
}
|
|
};
|
|
|
|
static const unsigned int ts_shift[] = TS_SHIFT;
|
|
|
|
static struct sh_dmae_pdata dma_platform_data = {
|
|
.slave = sh7372_dmae_slaves,
|
|
.slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
|
|
.channel = sh7372_dmae_channels,
|
|
.channel_num = ARRAY_SIZE(sh7372_dmae_channels),
|
|
.ts_low_shift = 3,
|
|
.ts_low_mask = 0x18,
|
|
.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
|
|
.ts_high_mask = 0x00300000,
|
|
.ts_shift = ts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
};
|
|
|
|
/* Resource order important! */
|
|
static struct resource sh7372_dmae0_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xfe008020,
|
|
.end = 0xfe00808f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMARSx */
|
|
.start = 0xfe009000,
|
|
.end = 0xfe00900b,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMA error IRQ */
|
|
.start = evt2irq(0x20c0),
|
|
.end = evt2irq(0x20c0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
/* IRQ for channels 0-5 */
|
|
.start = evt2irq(0x2000),
|
|
.end = evt2irq(0x20a0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
/* Resource order important! */
|
|
static struct resource sh7372_dmae1_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xfe018020,
|
|
.end = 0xfe01808f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMARSx */
|
|
.start = 0xfe019000,
|
|
.end = 0xfe01900b,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMA error IRQ */
|
|
.start = evt2irq(0x21c0),
|
|
.end = evt2irq(0x21c0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
/* IRQ for channels 0-5 */
|
|
.start = evt2irq(0x2100),
|
|
.end = evt2irq(0x21a0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
/* Resource order important! */
|
|
static struct resource sh7372_dmae2_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xfe028020,
|
|
.end = 0xfe02808f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMARSx */
|
|
.start = 0xfe029000,
|
|
.end = 0xfe02900b,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* DMA error IRQ */
|
|
.start = evt2irq(0x22c0),
|
|
.end = evt2irq(0x22c0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
/* IRQ for channels 0-5 */
|
|
.start = evt2irq(0x2200),
|
|
.end = evt2irq(0x22a0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dma0_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 0,
|
|
.resource = sh7372_dmae0_resources,
|
|
.num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
|
|
.dev = {
|
|
.platform_data = &dma_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dma1_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 1,
|
|
.resource = sh7372_dmae1_resources,
|
|
.num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
|
|
.dev = {
|
|
.platform_data = &dma_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dma2_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 2,
|
|
.resource = sh7372_dmae2_resources,
|
|
.num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
|
|
.dev = {
|
|
.platform_data = &dma_platform_data,
|
|
},
|
|
};
|
|
|
|
/*
|
|
* USB-DMAC
|
|
*/
|
|
|
|
unsigned int usbts_shift[] = {3, 4, 5};
|
|
|
|
enum {
|
|
XMIT_SZ_8BYTE = 0,
|
|
XMIT_SZ_16BYTE = 1,
|
|
XMIT_SZ_32BYTE = 2,
|
|
};
|
|
|
|
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
|
|
|
|
static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
|
|
{
|
|
.offset = 0,
|
|
}, {
|
|
.offset = 0x20,
|
|
},
|
|
};
|
|
|
|
/* USB DMAC0 */
|
|
static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
|
|
{
|
|
.slave_id = SHDMA_SLAVE_USB0_TX,
|
|
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_USB0_RX,
|
|
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
|
},
|
|
};
|
|
|
|
static struct sh_dmae_pdata usb_dma0_platform_data = {
|
|
.slave = sh7372_usb_dmae0_slaves,
|
|
.slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
|
|
.channel = sh7372_usb_dmae_channels,
|
|
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
|
|
.ts_low_shift = 6,
|
|
.ts_low_mask = 0xc0,
|
|
.ts_high_shift = 0,
|
|
.ts_high_mask = 0,
|
|
.ts_shift = usbts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(usbts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
.chcr_offset = 0x14,
|
|
.chcr_ie_bit = 1 << 5,
|
|
.dmaor_is_32bit = 1,
|
|
.needs_tend_set = 1,
|
|
.no_dmars = 1,
|
|
};
|
|
|
|
static struct resource sh7372_usb_dmae0_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xe68a0020,
|
|
.end = 0xe68a0064 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* VCR/SWR/DMICR */
|
|
.start = 0xe68a0000,
|
|
.end = 0xe68a0014 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* IRQ for channels */
|
|
.start = evt2irq(0x0a00),
|
|
.end = evt2irq(0x0a00),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device usb_dma0_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 3,
|
|
.resource = sh7372_usb_dmae0_resources,
|
|
.num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
|
|
.dev = {
|
|
.platform_data = &usb_dma0_platform_data,
|
|
},
|
|
};
|
|
|
|
/* USB DMAC1 */
|
|
static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
|
|
{
|
|
.slave_id = SHDMA_SLAVE_USB1_TX,
|
|
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_USB1_RX,
|
|
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
|
},
|
|
};
|
|
|
|
static struct sh_dmae_pdata usb_dma1_platform_data = {
|
|
.slave = sh7372_usb_dmae1_slaves,
|
|
.slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
|
|
.channel = sh7372_usb_dmae_channels,
|
|
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
|
|
.ts_low_shift = 6,
|
|
.ts_low_mask = 0xc0,
|
|
.ts_high_shift = 0,
|
|
.ts_high_mask = 0,
|
|
.ts_shift = usbts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(usbts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
.chcr_offset = 0x14,
|
|
.chcr_ie_bit = 1 << 5,
|
|
.dmaor_is_32bit = 1,
|
|
.needs_tend_set = 1,
|
|
.no_dmars = 1,
|
|
};
|
|
|
|
static struct resource sh7372_usb_dmae1_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xe68c0020,
|
|
.end = 0xe68c0064 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* VCR/SWR/DMICR */
|
|
.start = 0xe68c0000,
|
|
.end = 0xe68c0014 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* IRQ for channels */
|
|
.start = evt2irq(0x1d00),
|
|
.end = evt2irq(0x1d00),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device usb_dma1_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 4,
|
|
.resource = sh7372_usb_dmae1_resources,
|
|
.num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
|
|
.dev = {
|
|
.platform_data = &usb_dma1_platform_data,
|
|
},
|
|
};
|
|
|
|
/* VPU */
|
|
static struct uio_info vpu_platform_data = {
|
|
.name = "VPU5HG",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x980),
|
|
};
|
|
|
|
static struct resource vpu_resources[] = {
|
|
[0] = {
|
|
.name = "VPU",
|
|
.start = 0xfe900000,
|
|
.end = 0xfe900157,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device vpu_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &vpu_platform_data,
|
|
},
|
|
.resource = vpu_resources,
|
|
.num_resources = ARRAY_SIZE(vpu_resources),
|
|
};
|
|
|
|
/* VEU0 */
|
|
static struct uio_info veu0_platform_data = {
|
|
.name = "VEU0",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x700),
|
|
};
|
|
|
|
static struct resource veu0_resources[] = {
|
|
[0] = {
|
|
.name = "VEU0",
|
|
.start = 0xfe920000,
|
|
.end = 0xfe9200cb,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device veu0_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 1,
|
|
.dev = {
|
|
.platform_data = &veu0_platform_data,
|
|
},
|
|
.resource = veu0_resources,
|
|
.num_resources = ARRAY_SIZE(veu0_resources),
|
|
};
|
|
|
|
/* VEU1 */
|
|
static struct uio_info veu1_platform_data = {
|
|
.name = "VEU1",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x720),
|
|
};
|
|
|
|
static struct resource veu1_resources[] = {
|
|
[0] = {
|
|
.name = "VEU1",
|
|
.start = 0xfe924000,
|
|
.end = 0xfe9240cb,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device veu1_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 2,
|
|
.dev = {
|
|
.platform_data = &veu1_platform_data,
|
|
},
|
|
.resource = veu1_resources,
|
|
.num_resources = ARRAY_SIZE(veu1_resources),
|
|
};
|
|
|
|
/* VEU2 */
|
|
static struct uio_info veu2_platform_data = {
|
|
.name = "VEU2",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x740),
|
|
};
|
|
|
|
static struct resource veu2_resources[] = {
|
|
[0] = {
|
|
.name = "VEU2",
|
|
.start = 0xfe928000,
|
|
.end = 0xfe928307,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device veu2_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 3,
|
|
.dev = {
|
|
.platform_data = &veu2_platform_data,
|
|
},
|
|
.resource = veu2_resources,
|
|
.num_resources = ARRAY_SIZE(veu2_resources),
|
|
};
|
|
|
|
/* VEU3 */
|
|
static struct uio_info veu3_platform_data = {
|
|
.name = "VEU3",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x760),
|
|
};
|
|
|
|
static struct resource veu3_resources[] = {
|
|
[0] = {
|
|
.name = "VEU3",
|
|
.start = 0xfe92c000,
|
|
.end = 0xfe92c307,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device veu3_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 4,
|
|
.dev = {
|
|
.platform_data = &veu3_platform_data,
|
|
},
|
|
.resource = veu3_resources,
|
|
.num_resources = ARRAY_SIZE(veu3_resources),
|
|
};
|
|
|
|
/* JPU */
|
|
static struct uio_info jpu_platform_data = {
|
|
.name = "JPU",
|
|
.version = "0",
|
|
.irq = intcs_evt2irq(0x560),
|
|
};
|
|
|
|
static struct resource jpu_resources[] = {
|
|
[0] = {
|
|
.name = "JPU",
|
|
.start = 0xfe980000,
|
|
.end = 0xfe9902d3,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device jpu_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 5,
|
|
.dev = {
|
|
.platform_data = &jpu_platform_data,
|
|
},
|
|
.resource = jpu_resources,
|
|
.num_resources = ARRAY_SIZE(jpu_resources),
|
|
};
|
|
|
|
/* SPU2DSP0 */
|
|
static struct uio_info spu0_platform_data = {
|
|
.name = "SPU2DSP0",
|
|
.version = "0",
|
|
.irq = evt2irq(0x1800),
|
|
};
|
|
|
|
static struct resource spu0_resources[] = {
|
|
[0] = {
|
|
.name = "SPU2DSP0",
|
|
.start = 0xfe200000,
|
|
.end = 0xfe2fffff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device spu0_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 6,
|
|
.dev = {
|
|
.platform_data = &spu0_platform_data,
|
|
},
|
|
.resource = spu0_resources,
|
|
.num_resources = ARRAY_SIZE(spu0_resources),
|
|
};
|
|
|
|
/* SPU2DSP1 */
|
|
static struct uio_info spu1_platform_data = {
|
|
.name = "SPU2DSP1",
|
|
.version = "0",
|
|
.irq = evt2irq(0x1820),
|
|
};
|
|
|
|
static struct resource spu1_resources[] = {
|
|
[0] = {
|
|
.name = "SPU2DSP1",
|
|
.start = 0xfe300000,
|
|
.end = 0xfe3fffff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device spu1_device = {
|
|
.name = "uio_pdrv_genirq",
|
|
.id = 7,
|
|
.dev = {
|
|
.platform_data = &spu1_platform_data,
|
|
},
|
|
.resource = spu1_resources,
|
|
.num_resources = ARRAY_SIZE(spu1_resources),
|
|
};
|
|
|
|
static struct platform_device *sh7372_early_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&scif3_device,
|
|
&scif4_device,
|
|
&scif5_device,
|
|
&scif6_device,
|
|
&cmt2_device,
|
|
&tmu00_device,
|
|
&tmu01_device,
|
|
};
|
|
|
|
static struct platform_device *sh7372_late_devices[] __initdata = {
|
|
&iic0_device,
|
|
&iic1_device,
|
|
&dma0_device,
|
|
&dma1_device,
|
|
&dma2_device,
|
|
&usb_dma0_device,
|
|
&usb_dma1_device,
|
|
&vpu_device,
|
|
&veu0_device,
|
|
&veu1_device,
|
|
&veu2_device,
|
|
&veu3_device,
|
|
&jpu_device,
|
|
&spu0_device,
|
|
&spu1_device,
|
|
};
|
|
|
|
void __init sh7372_add_standard_devices(void)
|
|
{
|
|
sh7372_init_pm_domain(&sh7372_a4lc);
|
|
sh7372_init_pm_domain(&sh7372_a4mp);
|
|
sh7372_init_pm_domain(&sh7372_d4);
|
|
sh7372_init_pm_domain(&sh7372_a4r);
|
|
sh7372_init_pm_domain(&sh7372_a3rv);
|
|
sh7372_init_pm_domain(&sh7372_a3ri);
|
|
sh7372_init_pm_domain(&sh7372_a3sg);
|
|
sh7372_init_pm_domain(&sh7372_a3sp);
|
|
|
|
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
|
|
sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
|
|
|
|
platform_add_devices(sh7372_early_devices,
|
|
ARRAY_SIZE(sh7372_early_devices));
|
|
|
|
platform_add_devices(sh7372_late_devices,
|
|
ARRAY_SIZE(sh7372_late_devices));
|
|
|
|
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
|
|
sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
|
|
}
|
|
|
|
void __init sh7372_add_early_devices(void)
|
|
{
|
|
early_platform_add_devices(sh7372_early_devices,
|
|
ARRAY_SIZE(sh7372_early_devices));
|
|
}
|