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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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09cee1ab0e
According to replacing the name of EXYNOS clock registers, this patch updates exynos4210-cpufreq.c file where it is used. Cc: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
305 lines
7.3 KiB
C
305 lines
7.3 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4210 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <mach/regs-clock.h>
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#include <mach/cpufreq.h>
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#define CPUFREQ_LEVEL_END L5
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static int max_support_idx = L0;
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static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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struct cpufreq_clkdiv {
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unsigned int index;
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unsigned int clkdiv;
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};
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static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
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1250000, 1150000, 1050000, 975000, 950000,
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};
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static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
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static struct cpufreq_frequency_table exynos4210_freq_table[] = {
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{L0, 1200*1000},
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{L1, 1000*1000},
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{L2, 800*1000},
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{L3, 500*1000},
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{L4, 200*1000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL }
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*/
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/* ARM L0: 1200MHz */
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{ 0, 3, 7, 3, 4, 1, 7 },
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/* ARM L1: 1000MHz */
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{ 0, 3, 7, 3, 4, 1, 7 },
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/* ARM L2: 800MHz */
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{ 0, 3, 7, 3, 3, 1, 7 },
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/* ARM L3: 500MHz */
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{ 0, 3, 7, 3, 3, 1, 7 },
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/* ARM L4: 200MHz */
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{ 0, 1, 3, 1, 3, 1, 0 },
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};
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static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVCOPY, DIVHPM }
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*/
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/* ARM L0: 1200MHz */
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{ 5, 0 },
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/* ARM L1: 1000MHz */
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{ 4, 0 },
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/* ARM L2: 800MHz */
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{ 3, 0 },
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/* ARM L3: 500MHz */
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{ 3, 0 },
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/* ARM L4: 200MHz */
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{ 3, 0 },
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};
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static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* APLL FOUT L0: 1200MHz */
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((150 << 16) | (3 << 8) | 1),
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/* APLL FOUT L1: 1000MHz */
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((250 << 16) | (6 << 8) | 1),
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/* APLL FOUT L2: 800MHz */
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((200 << 16) | (6 << 8) | 1),
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/* APLL FOUT L3: 500MHz */
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((250 << 16) | (6 << 8) | 2),
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/* APLL FOUT L4: 200MHz */
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((200 << 16) | (6 << 8) | 3),
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};
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static void exynos4210_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = exynos4210_clkdiv_table[div_index].clkdiv;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
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tmp &= ~((0x7 << 4) | 0x7);
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tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
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(clkdiv_cpu1[div_index][1] << 0));
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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}
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static void exynos4210_set_apll(unsigned int index)
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{
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unsigned int tmp;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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__raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= exynos4210_apll_pms_table[index];
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
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{
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unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
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unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
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return (old_pm == new_pm) ? 0 : 1;
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}
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static void exynos4210_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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if (!exynos4210_pms_change(old_index, new_index)) {
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/* 1. Change the system clock divider values */
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exynos4210_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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exynos4210_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4210_set_apll(new_index);
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}
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} else if (old_index < new_index) {
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if (!exynos4210_pms_change(old_index, new_index)) {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 2. Change the system clock divider values */
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exynos4210_set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the apll m,p,s value */
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exynos4210_set_apll(new_index);
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/* 2. Change the system clock divider values */
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exynos4210_set_clkdiv(new_index);
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}
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}
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}
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int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
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{
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int i;
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unsigned int tmp;
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unsigned long rate;
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "moutcore");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
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for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
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tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
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EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
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EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
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EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
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EXYNOS4_CLKDIV_CPU0_ATB_MASK |
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EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
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EXYNOS4_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
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exynos4210_clkdiv_table[i].clkdiv = tmp;
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}
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info->mpll_freq_khz = rate;
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info->pm_lock_idx = L2;
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info->pll_safe_idx = L2;
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info->max_support_idx = max_support_idx;
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info->min_support_idx = min_support_idx;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos4210_volt_table;
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info->freq_table = exynos4210_freq_table;
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info->set_freq = exynos4210_set_frequency;
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info->need_apll_change = exynos4210_pms_change;
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return 0;
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err_mout_apll:
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if (!IS_ERR(mout_mpll))
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clk_put(mout_mpll);
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err_mout_mpll:
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if (!IS_ERR(moutcore))
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clk_put(moutcore);
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err_moutcore:
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if (!IS_ERR(cpu_clk))
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clk_put(cpu_clk);
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pr_debug("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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EXPORT_SYMBOL(exynos4210_cpufreq_init);
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