mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:46:44 +07:00
e18ce34654
flags used within drivers for indicating tx and rx flow control are defined in 4 drivers (and probably more), move these constants to mii.h. The 3 SMSC drivers use the same constants (FLOW_CTRL_TX), but TG3 uses TG3_FLOW_CTRL_TX, so this patch also renames the constants within TG3. Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
276 lines
8.3 KiB
C
276 lines
8.3 KiB
C
/***************************************************************************
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*
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* Copyright (C) 2007,2008 SMSC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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***************************************************************************
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*/
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#ifndef _SMSC9420_H
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#define _SMSC9420_H
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#define TX_RING_SIZE (32)
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#define RX_RING_SIZE (128)
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/* interrupt deassertion in multiples of 10us */
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#define INT_DEAS_TIME (50)
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#define NAPI_WEIGHT (64)
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#define SMSC_BAR (3)
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#ifdef __BIG_ENDIAN
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/* Register set is duplicated for BE at an offset of 0x200 */
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#define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
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#else
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#define LAN9420_CPSR_ENDIAN_OFFSET (0)
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#endif
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#define PCI_VENDOR_ID_9420 (0x1055)
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#define PCI_DEVICE_ID_9420 (0xE420)
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#define LAN_REGISTER_EXTENT (0x400)
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#define SMSC9420_EEPROM_SIZE ((u32)11)
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#define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
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/***********************************************/
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/* DMA Controller Control and Status Registers */
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/***********************************************/
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#define BUS_MODE (0x00)
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#define BUS_MODE_SWR_ (BIT(0))
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#define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
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#define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
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#define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
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#define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
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#define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
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#define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
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#define BUS_MODE_DBO_ (BIT(20))
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#define TX_POLL_DEMAND (0x04)
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#define RX_POLL_DEMAND (0x08)
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#define RX_BASE_ADDR (0x0C)
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#define TX_BASE_ADDR (0x10)
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#define DMAC_STATUS (0x14)
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#define DMAC_STS_TS_ (7 << 20)
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#define DMAC_STS_RS_ (7 << 17)
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#define DMAC_STS_NIS_ (BIT(16))
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#define DMAC_STS_AIS_ (BIT(15))
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#define DMAC_STS_RWT_ (BIT(9))
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#define DMAC_STS_RXPS_ (BIT(8))
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#define DMAC_STS_RXBU_ (BIT(7))
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#define DMAC_STS_RX_ (BIT(6))
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#define DMAC_STS_TXUNF_ (BIT(5))
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#define DMAC_STS_TXBU_ (BIT(2))
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#define DMAC_STS_TXPS_ (BIT(1))
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#define DMAC_STS_TX_ (BIT(0))
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#define DMAC_CONTROL (0x18)
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#define DMAC_CONTROL_TTM_ (BIT(22))
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#define DMAC_CONTROL_SF_ (BIT(21))
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#define DMAC_CONTROL_ST_ (BIT(13))
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#define DMAC_CONTROL_OSF_ (BIT(2))
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#define DMAC_CONTROL_SR_ (BIT(1))
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#define DMAC_INTR_ENA (0x1C)
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#define DMAC_INTR_ENA_NIS_ (BIT(16))
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#define DMAC_INTR_ENA_AIS_ (BIT(15))
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#define DMAC_INTR_ENA_RWT_ (BIT(9))
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#define DMAC_INTR_ENA_RXPS_ (BIT(8))
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#define DMAC_INTR_ENA_RXBU_ (BIT(7))
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#define DMAC_INTR_ENA_RX_ (BIT(6))
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#define DMAC_INTR_ENA_TXBU_ (BIT(2))
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#define DMAC_INTR_ENA_TXPS_ (BIT(1))
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#define DMAC_INTR_ENA_TX_ (BIT(0))
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#define MISS_FRAME_CNTR (0x20)
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#define TX_BUFF_ADDR (0x50)
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#define RX_BUFF_ADDR (0x54)
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/* Transmit Descriptor Bit Defs */
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#define TDES0_OWN_ (0x80000000)
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#define TDES0_ERROR_SUMMARY_ (0x00008000)
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#define TDES0_LOSS_OF_CARRIER_ (0x00000800)
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#define TDES0_NO_CARRIER_ (0x00000400)
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#define TDES0_LATE_COLLISION_ (0x00000200)
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#define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100)
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#define TDES0_HEARTBEAT_FAIL_ (0x00000080)
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#define TDES0_COLLISION_COUNT_MASK_ (0x00000078)
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#define TDES0_COLLISION_COUNT_SHFT_ (3)
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#define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004)
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#define TDES0_DEFERRED_ (0x00000001)
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#define TDES1_IC_ 0x80000000
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#define TDES1_LS_ 0x40000000
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#define TDES1_FS_ 0x20000000
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#define TDES1_TXCSEN_ 0x08000000
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#define TDES1_TER_ (BIT(25))
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#define TDES1_TCH_ 0x01000000
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/* Receive Descriptor 0 Bit Defs */
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#define RDES0_OWN_ (0x80000000)
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#define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000)
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#define RDES0_FRAME_LENGTH_SHFT_ (16)
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#define RDES0_ERROR_SUMMARY_ (0x00008000)
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#define RDES0_DESCRIPTOR_ERROR_ (0x00004000)
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#define RDES0_LENGTH_ERROR_ (0x00001000)
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#define RDES0_RUNT_FRAME_ (0x00000800)
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#define RDES0_MULTICAST_FRAME_ (0x00000400)
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#define RDES0_FIRST_DESCRIPTOR_ (0x00000200)
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#define RDES0_LAST_DESCRIPTOR_ (0x00000100)
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#define RDES0_FRAME_TOO_LONG_ (0x00000080)
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#define RDES0_COLLISION_SEEN_ (0x00000040)
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#define RDES0_FRAME_TYPE_ (0x00000020)
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#define RDES0_WATCHDOG_TIMEOUT_ (0x00000010)
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#define RDES0_MII_ERROR_ (0x00000008)
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#define RDES0_DRIBBLING_BIT_ (0x00000004)
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#define RDES0_CRC_ERROR_ (0x00000002)
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/* Receive Descriptor 1 Bit Defs */
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#define RDES1_RER_ (0x02000000)
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/***********************************************/
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/* MAC Control and Status Registers */
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/***********************************************/
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#define MAC_CR (0x80)
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#define MAC_CR_RXALL_ (0x80000000)
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#define MAC_CR_DIS_RXOWN_ (0x00800000)
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#define MAC_CR_LOOPBK_ (0x00200000)
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#define MAC_CR_FDPX_ (0x00100000)
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#define MAC_CR_MCPAS_ (0x00080000)
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#define MAC_CR_PRMS_ (0x00040000)
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#define MAC_CR_INVFILT_ (0x00020000)
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#define MAC_CR_PASSBAD_ (0x00010000)
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#define MAC_CR_HFILT_ (0x00008000)
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#define MAC_CR_HPFILT_ (0x00002000)
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#define MAC_CR_LCOLL_ (0x00001000)
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#define MAC_CR_DIS_BCAST_ (0x00000800)
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#define MAC_CR_DIS_RTRY_ (0x00000400)
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#define MAC_CR_PADSTR_ (0x00000100)
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#define MAC_CR_BOLMT_MSK (0x000000C0)
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#define MAC_CR_MFCHK_ (0x00000020)
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#define MAC_CR_TXEN_ (0x00000008)
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#define MAC_CR_RXEN_ (0x00000004)
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#define ADDRH (0x84)
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#define ADDRL (0x88)
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#define HASHH (0x8C)
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#define HASHL (0x90)
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#define MII_ACCESS (0x94)
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#define MII_ACCESS_MII_BUSY_ (0x00000001)
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#define MII_ACCESS_MII_WRITE_ (0x00000002)
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#define MII_ACCESS_MII_READ_ (0x00000000)
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#define MII_ACCESS_INDX_MSK_ (0x000007C0)
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#define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0)
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#define MII_ACCESS_INDX_SHFT_CNT (6)
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#define MII_ACCESS_PHYADDR_SHFT_CNT (11)
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#define MII_DATA (0x98)
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#define FLOW (0x9C)
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#define VLAN1 (0xA0)
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#define VLAN2 (0xA4)
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#define WUFF (0xA8)
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#define WUCSR (0xAC)
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#define COE_CR (0xB0)
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#define TX_COE_EN (0x00010000)
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#define RX_COE_MODE (0x00000002)
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#define RX_COE_EN (0x00000001)
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/***********************************************/
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/* System Control and Status Registers */
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/***********************************************/
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#define ID_REV (0xC0)
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#define INT_CTL (0xC4)
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#define INT_CTL_SW_INT_EN_ (0x00008000)
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#define INT_CTL_SBERR_INT_EN_ (1 << 12)
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#define INT_CTL_MBERR_INT_EN_ (1 << 13)
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#define INT_CTL_GPT_INT_EN_ (0x00000008)
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#define INT_CTL_PHY_INT_EN_ (0x00000004)
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#define INT_CTL_WAKE_INT_EN_ (0x00000002)
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#define INT_STAT (0xC8)
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#define INT_STAT_SW_INT_ (1 << 15)
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#define INT_STAT_MBERR_INT_ (1 << 13)
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#define INT_STAT_SBERR_INT_ (1 << 12)
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#define INT_STAT_GPT_INT_ (1 << 3)
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#define INT_STAT_PHY_INT_ (0x00000004)
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#define INT_STAT_WAKE_INT_ (0x00000002)
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#define INT_STAT_DMAC_INT_ (0x00000001)
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#define INT_CFG (0xCC)
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#define INT_CFG_IRQ_INT_ (0x00080000)
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#define INT_CFG_IRQ_EN_ (0x00040000)
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#define INT_CFG_INT_DEAS_CLR_ (0x00000200)
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#define INT_CFG_INT_DEAS_MASK (0x000000FF)
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#define GPIO_CFG (0xD0)
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#define GPIO_CFG_LED_3_ (0x40000000)
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#define GPIO_CFG_LED_2_ (0x20000000)
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#define GPIO_CFG_LED_1_ (0x10000000)
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#define GPIO_CFG_EEPR_EN_ (0x00700000)
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#define GPT_CFG (0xD4)
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#define GPT_CFG_TIMER_EN_ (0x20000000)
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#define GPT_CNT (0xD8)
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#define BUS_CFG (0xDC)
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#define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25)
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#define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25)
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#define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25)
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#define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25)
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#define PMT_CTRL (0xE0)
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#define FREE_RUN (0xF4)
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#define E2P_CMD (0xF8)
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#define E2P_CMD_EPC_BUSY_ (0x80000000)
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#define E2P_CMD_EPC_CMD_ (0x70000000)
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#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
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#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
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#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
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#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
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#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
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#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
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#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
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#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
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#define E2P_CMD_EPC_TIMEOUT_ (0x00000200)
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#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100)
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#define E2P_CMD_EPC_ADDR_ (0x000000FF)
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#define E2P_DATA (0xFC)
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#define E2P_DATA_EEPROM_DATA_ (0x000000FF)
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#endif /* _SMSC9420_H */
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