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26372d0973
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
83 lines
3.1 KiB
Plaintext
83 lines
3.1 KiB
Plaintext
-----------------------------------------------------------------
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Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
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-----------------------------------------------------------------
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The zynqmp-firmware node describes the interface to platform firmware.
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ZynqMP has an interface to communicate with secure firmware. Firmware
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driver provides an interface to firmware APIs. Interface APIs can be
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used by any driver to communicate to PMUFW(Platform Management Unit).
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These requests include clock management, pin control, device control,
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power management service, FPGA service and other platform management
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services.
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Required properties:
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- compatible: Must contain: "xlnx,zynqmp-firmware"
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- method: The method of calling the PM-API firmware layer.
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Permitted values are:
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- "smc" : SMC #0, following the SMCCC
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- "hvc" : HVC #0, following the SMCCC
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--------------------------------------------------------------------------
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Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
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Zynq MPSoC firmware interface
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--------------------------------------------------------------------------
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The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
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tree. It reads required input clock frequencies from the devicetree and acts
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as clock provider for all clock consumers of PS clocks.
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See clock_bindings.txt for more information on the generic clock bindings.
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Required properties:
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- #clock-cells: Must be 1
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- compatible: Must contain: "xlnx,zynqmp-clk"
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- clocks: List of clock specifiers which are external input
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clocks to the given clock controller. Please refer
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the next section to find the input clocks for a
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given controller.
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- clock-names: List of clock names which are exteral input clocks
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to the given clock controller. Please refer to the
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clock bindings for more details.
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Input clocks for zynqmp Ultrascale+ clock controller:
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The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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inputs. These required clock inputs are:
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- pss_ref_clk (PS reference clock)
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- video_clk (reference clock for video system )
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- pss_alt_ref_clk (alternative PS reference clock)
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- aux_ref_clk
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- gt_crx_ref_clk (transceiver reference clock)
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The following strings are optional parameters to the 'clock-names' property in
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order to provide an optional (E)MIO clock source:
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- swdt0_ext_clk
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- swdt1_ext_clk
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- gem0_emio_clk
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- gem1_emio_clk
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- gem2_emio_clk
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- gem3_emio_clk
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- mio_clk_XX # with XX = 00..77
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- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
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Output clocks are registered based on clock information received
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from firmware. Output clocks indexes are mentioned in
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include/dt-bindings/clock/xlnx,zynqmp-clk.h.
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-------
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Example
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-------
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firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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zynqmp_clk: clock-controller {
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clk";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
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};
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};
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};
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