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-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAl0siFoUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vzi9A//S4jRyyZrgUr88Az0GbgMhE4b3yqc uL7om/Sf+443gG6C+aKkZSM/IE9hrbyIKuYq7GGxDkzZ/HkucZo2yIuAHkPgG4ik QQYJ8fJsmMq1bUht87c1ZZwGP0++Deq/Ns2+VNy/WBYqKLulnV0DvEEaJgPs9C5D ppwccGdo6UghiujBTpE4ddUBjFjjURWqT6wSnMRDQ4EGwfUhG0MWwwHKI4hbBuaL N6refuggdYyUUX5FeUOHa6VF6uTnSSAQ75k+40n4nljdayqoumHLskst77o9q5ZI oXjdpwgmuEqYhfp03HEA4Xo/bBxiRj76NuTiEMKvPokxjpanwbLrdV0GhF0OIlM0 rp1NOI1w+vppFrU+rc2gtq+7hYXFmvdhjS29hFLeD91PP36N5d29jW5NVFpm7GCm n4TMGAOsu8RB+bNua6ZbZVcDk2EnPgQeIcM0ZPoBtPK19Fg/rScdEU4u/aFE1Y0Q C+Ks7D1qCvFpHzl/xAg0oo9v/jFsWef3qnQWOzot964Zz4W4NSVvB9Ox6Vbfj6C4 v331LJmlPxG8fxBNA3q28FrTxcG1NW6sgo3WY9VoSp/vc0aqaPKhm7sbraTt5IrI TwqA/WhnAHv90MQCGFcofANyYTkjPkKk2QBFK6b0suoAmVdwVWWELi1WaZ+HdvgQ JP7YpmC2cXcQBPk= =ZGxL -----END PGP SIGNATURE----- Merge tag 'pci-v5.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration changes: - Evaluate PCI Boot Configuration _DSM to learn if firmware wants us to preserve its resource assignments (Benjamin Herrenschmidt) - Simplify resource distribution (Nicholas Johnson) - Decode 32 GT/s link speed (Gustavo Pimentel) Virtualization: - Fix incorrect caching of VF config space size (Alex Williamson) - Fix VF driver probing sysfs knobs (Alex Williamson) Peer-to-peer DMA: - Fix dma_virt_ops check (Logan Gunthorpe) Altera host bridge driver: - Allow building as module (Ley Foon Tan) Armada 8K host bridge driver: - add PHYs support (Miquel Raynal) DesignWare host bridge driver: - Export APIs to support removable loadable module (Vidya Sagar) - Enable Relaxed Ordering erratum workaround only on Tegra20 & Tegra30 (Vidya Sagar) Hyper-V host bridge driver: - Fix use-after-free in eject (Dexuan Cui) Mobiveil host bridge driver: - Clean up and fix many issues, including non-identify mapped windows, 64-bit windows, multi-MSI, class code, INTx clearing (Hou Zhiqiang) Qualcomm host bridge driver: - Use clk bulk API for 2.4.0 controllers (Bjorn Andersson) - Add QCS404 support (Bjorn Andersson) - Assert PERST for at least 100ms (Niklas Cassel) R-Car host bridge driver: - Add r8a774a1 DT support (Biju Das) Tegra host bridge driver: - Add support for Gen2, opportunistic UpdateFC and ACK (PCIe protocol details) AER, GPIO-based PERST# (Manikanta Maddireddy) - Fix many issues, including power-on failure cases, interrupt masking in suspend, UPHY settings, AFI dynamic clock gating, pending DLL transactions (Manikanta Maddireddy) Xilinx host bridge driver: - Fix NWL Multi-MSI programming (Bharat Kumar Gogada) Endpoint support: - Fix 64bit BAR support (Alan Mikhak) - Fix pcitest build issues (Alan Mikhak, Andy Shevchenko) Bug fixes: - Fix NVIDIA GPU multi-function power dependencies (Abhishek Sahu) - Fix NVIDIA GPU HDA enablement issue (Lukas Wunner) - Ignore lockdep for sysfs "remove" (Marek Vasut) Misc: - Convert docs to reST (Changbin Du, Mauro Carvalho Chehab)" * tag 'pci-v5.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (107 commits) PCI: Enable NVIDIA HDA controllers tools: PCI: Fix installation when `make tools/pci_install` PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: Fix typos and whitespace errors PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr() PCI: mobiveil: Fix infinite-loop in the INTx handling function PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup PCI: mobiveil: Clear the control fields before updating it PCI: mobiveil: Add configured inbound windows counter PCI: mobiveil: Fix the valid check for inbound and outbound windows PCI: mobiveil: Clean-up program_{ib/ob}_windows() PCI: mobiveil: Remove an unnecessary return value check PCI: mobiveil: Fix error return values PCI: mobiveil: Refactor the MEM/IO outbound window initialization PCI: mobiveil: Make some register updates more readable PCI: mobiveil: Reformat the code for readability dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional ...
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=======================
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Energy Aware Scheduling
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=======================
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1. Introduction
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---------------
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Energy Aware Scheduling (or EAS) gives the scheduler the ability to predict
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the impact of its decisions on the energy consumed by CPUs. EAS relies on an
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Energy Model (EM) of the CPUs to select an energy efficient CPU for each task,
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with a minimal impact on throughput. This document aims at providing an
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introduction on how EAS works, what are the main design decisions behind it, and
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details what is needed to get it to run.
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Before going any further, please note that at the time of writing::
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/!\ EAS does not support platforms with symmetric CPU topologies /!\
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EAS operates only on heterogeneous CPU topologies (such as Arm big.LITTLE)
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because this is where the potential for saving energy through scheduling is
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the highest.
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The actual EM used by EAS is _not_ maintained by the scheduler, but by a
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dedicated framework. For details about this framework and what it provides,
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please refer to its documentation (see Documentation/power/energy-model.rst).
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2. Background and Terminology
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-----------------------------
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To make it clear from the start:
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- energy = [joule] (resource like a battery on powered devices)
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- power = energy/time = [joule/second] = [watt]
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The goal of EAS is to minimize energy, while still getting the job done. That
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is, we want to maximize::
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performance [inst/s]
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--------------------
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power [W]
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which is equivalent to minimizing::
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energy [J]
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-----------
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instruction
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while still getting 'good' performance. It is essentially an alternative
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optimization objective to the current performance-only objective for the
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scheduler. This alternative considers two objectives: energy-efficiency and
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performance.
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The idea behind introducing an EM is to allow the scheduler to evaluate the
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implications of its decisions rather than blindly applying energy-saving
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techniques that may have positive effects only on some platforms. At the same
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time, the EM must be as simple as possible to minimize the scheduler latency
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impact.
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In short, EAS changes the way CFS tasks are assigned to CPUs. When it is time
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for the scheduler to decide where a task should run (during wake-up), the EM
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is used to break the tie between several good CPU candidates and pick the one
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that is predicted to yield the best energy consumption without harming the
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system's throughput. The predictions made by EAS rely on specific elements of
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knowledge about the platform's topology, which include the 'capacity' of CPUs,
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and their respective energy costs.
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3. Topology information
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-----------------------
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EAS (as well as the rest of the scheduler) uses the notion of 'capacity' to
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differentiate CPUs with different computing throughput. The 'capacity' of a CPU
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represents the amount of work it can absorb when running at its highest
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frequency compared to the most capable CPU of the system. Capacity values are
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normalized in a 1024 range, and are comparable with the utilization signals of
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tasks and CPUs computed by the Per-Entity Load Tracking (PELT) mechanism. Thanks
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to capacity and utilization values, EAS is able to estimate how big/busy a
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task/CPU is, and to take this into consideration when evaluating performance vs
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energy trade-offs. The capacity of CPUs is provided via arch-specific code
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through the arch_scale_cpu_capacity() callback.
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The rest of platform knowledge used by EAS is directly read from the Energy
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Model (EM) framework. The EM of a platform is composed of a power cost table
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per 'performance domain' in the system (see Documentation/power/energy-model.rst
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for futher details about performance domains).
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The scheduler manages references to the EM objects in the topology code when the
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scheduling domains are built, or re-built. For each root domain (rd), the
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scheduler maintains a singly linked list of all performance domains intersecting
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the current rd->span. Each node in the list contains a pointer to a struct
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em_perf_domain as provided by the EM framework.
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The lists are attached to the root domains in order to cope with exclusive
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cpuset configurations. Since the boundaries of exclusive cpusets do not
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necessarily match those of performance domains, the lists of different root
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domains can contain duplicate elements.
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Example 1.
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Let us consider a platform with 12 CPUs, split in 3 performance domains
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(pd0, pd4 and pd8), organized as follows::
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CPUs: 0 1 2 3 4 5 6 7 8 9 10 11
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PDs: |--pd0--|--pd4--|---pd8---|
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RDs: |----rd1----|-----rd2-----|
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Now, consider that userspace decided to split the system with two
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exclusive cpusets, hence creating two independent root domains, each
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containing 6 CPUs. The two root domains are denoted rd1 and rd2 in the
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above figure. Since pd4 intersects with both rd1 and rd2, it will be
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present in the linked list '->pd' attached to each of them:
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* rd1->pd: pd0 -> pd4
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* rd2->pd: pd4 -> pd8
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Please note that the scheduler will create two duplicate list nodes for
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pd4 (one for each list). However, both just hold a pointer to the same
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shared data structure of the EM framework.
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Since the access to these lists can happen concurrently with hotplug and other
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things, they are protected by RCU, like the rest of topology structures
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manipulated by the scheduler.
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EAS also maintains a static key (sched_energy_present) which is enabled when at
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least one root domain meets all conditions for EAS to start. Those conditions
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are summarized in Section 6.
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4. Energy-Aware task placement
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------------------------------
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EAS overrides the CFS task wake-up balancing code. It uses the EM of the
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platform and the PELT signals to choose an energy-efficient target CPU during
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wake-up balance. When EAS is enabled, select_task_rq_fair() calls
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find_energy_efficient_cpu() to do the placement decision. This function looks
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for the CPU with the highest spare capacity (CPU capacity - CPU utilization) in
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each performance domain since it is the one which will allow us to keep the
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frequency the lowest. Then, the function checks if placing the task there could
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save energy compared to leaving it on prev_cpu, i.e. the CPU where the task ran
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in its previous activation.
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find_energy_efficient_cpu() uses compute_energy() to estimate what will be the
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energy consumed by the system if the waking task was migrated. compute_energy()
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looks at the current utilization landscape of the CPUs and adjusts it to
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'simulate' the task migration. The EM framework provides the em_pd_energy() API
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which computes the expected energy consumption of each performance domain for
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the given utilization landscape.
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An example of energy-optimized task placement decision is detailed below.
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Example 2.
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Let us consider a (fake) platform with 2 independent performance domains
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composed of two CPUs each. CPU0 and CPU1 are little CPUs; CPU2 and CPU3
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are big.
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The scheduler must decide where to place a task P whose util_avg = 200
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and prev_cpu = 0.
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The current utilization landscape of the CPUs is depicted on the graph
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below. CPUs 0-3 have a util_avg of 400, 100, 600 and 500 respectively
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Each performance domain has three Operating Performance Points (OPPs).
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The CPU capacity and power cost associated with each OPP is listed in
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the Energy Model table. The util_avg of P is shown on the figures
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below as 'PP'::
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CPU util.
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1024 - - - - - - - Energy Model
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+-----------+-------------+
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| Little | Big |
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768 ============= +-----+-----+------+------+
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| Cap | Pwr | Cap | Pwr |
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+-----+-----+------+------+
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512 =========== - ##- - - - - | 170 | 50 | 512 | 400 |
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## ## | 341 | 150 | 768 | 800 |
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341 -PP - - - - ## ## | 512 | 300 | 1024 | 1700 |
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PP ## ## +-----+-----+------+------+
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170 -## - - - - ## ##
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## ## ## ##
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------------ -------------
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CPU0 CPU1 CPU2 CPU3
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Current OPP: ===== Other OPP: - - - util_avg (100 each): ##
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find_energy_efficient_cpu() will first look for the CPUs with the
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maximum spare capacity in the two performance domains. In this example,
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CPU1 and CPU3. Then it will estimate the energy of the system if P was
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placed on either of them, and check if that would save some energy
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compared to leaving P on CPU0. EAS assumes that OPPs follow utilization
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(which is coherent with the behaviour of the schedutil CPUFreq
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governor, see Section 6. for more details on this topic).
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**Case 1. P is migrated to CPU1**::
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1024 - - - - - - -
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Energy calculation:
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768 ============= * CPU0: 200 / 341 * 150 = 88
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* CPU1: 300 / 341 * 150 = 131
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* CPU2: 600 / 768 * 800 = 625
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512 - - - - - - - ##- - - - - * CPU3: 500 / 768 * 800 = 520
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## ## => total_energy = 1364
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341 =========== ## ##
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PP ## ##
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170 -## - - PP- ## ##
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## ## ## ##
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------------ -------------
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CPU0 CPU1 CPU2 CPU3
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**Case 2. P is migrated to CPU3**::
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1024 - - - - - - -
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Energy calculation:
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768 ============= * CPU0: 200 / 341 * 150 = 88
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* CPU1: 100 / 341 * 150 = 43
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PP * CPU2: 600 / 768 * 800 = 625
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512 - - - - - - - ##- - -PP - * CPU3: 700 / 768 * 800 = 729
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## ## => total_energy = 1485
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341 =========== ## ##
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## ##
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170 -## - - - - ## ##
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## ## ## ##
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------------ -------------
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CPU0 CPU1 CPU2 CPU3
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**Case 3. P stays on prev_cpu / CPU 0**::
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1024 - - - - - - -
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Energy calculation:
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768 ============= * CPU0: 400 / 512 * 300 = 234
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* CPU1: 100 / 512 * 300 = 58
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* CPU2: 600 / 768 * 800 = 625
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512 =========== - ##- - - - - * CPU3: 500 / 768 * 800 = 520
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## ## => total_energy = 1437
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341 -PP - - - - ## ##
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PP ## ##
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170 -## - - - - ## ##
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## ## ## ##
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------------ -------------
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CPU0 CPU1 CPU2 CPU3
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From these calculations, the Case 1 has the lowest total energy. So CPU 1
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is be the best candidate from an energy-efficiency standpoint.
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Big CPUs are generally more power hungry than the little ones and are thus used
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mainly when a task doesn't fit the littles. However, little CPUs aren't always
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necessarily more energy-efficient than big CPUs. For some systems, the high OPPs
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of the little CPUs can be less energy-efficient than the lowest OPPs of the
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bigs, for example. So, if the little CPUs happen to have enough utilization at
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a specific point in time, a small task waking up at that moment could be better
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of executing on the big side in order to save energy, even though it would fit
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on the little side.
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And even in the case where all OPPs of the big CPUs are less energy-efficient
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than those of the little, using the big CPUs for a small task might still, under
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specific conditions, save energy. Indeed, placing a task on a little CPU can
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result in raising the OPP of the entire performance domain, and that will
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increase the cost of the tasks already running there. If the waking task is
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placed on a big CPU, its own execution cost might be higher than if it was
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running on a little, but it won't impact the other tasks of the little CPUs
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which will keep running at a lower OPP. So, when considering the total energy
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consumed by CPUs, the extra cost of running that one task on a big core can be
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smaller than the cost of raising the OPP on the little CPUs for all the other
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tasks.
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The examples above would be nearly impossible to get right in a generic way, and
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for all platforms, without knowing the cost of running at different OPPs on all
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CPUs of the system. Thanks to its EM-based design, EAS should cope with them
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correctly without too many troubles. However, in order to ensure a minimal
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impact on throughput for high-utilization scenarios, EAS also implements another
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mechanism called 'over-utilization'.
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5. Over-utilization
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-------------------
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From a general standpoint, the use-cases where EAS can help the most are those
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involving a light/medium CPU utilization. Whenever long CPU-bound tasks are
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being run, they will require all of the available CPU capacity, and there isn't
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much that can be done by the scheduler to save energy without severly harming
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throughput. In order to avoid hurting performance with EAS, CPUs are flagged as
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'over-utilized' as soon as they are used at more than 80% of their compute
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capacity. As long as no CPUs are over-utilized in a root domain, load balancing
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is disabled and EAS overridess the wake-up balancing code. EAS is likely to load
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the most energy efficient CPUs of the system more than the others if that can be
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done without harming throughput. So, the load-balancer is disabled to prevent
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it from breaking the energy-efficient task placement found by EAS. It is safe to
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do so when the system isn't overutilized since being below the 80% tipping point
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implies that:
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a. there is some idle time on all CPUs, so the utilization signals used by
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EAS are likely to accurately represent the 'size' of the various tasks
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in the system;
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b. all tasks should already be provided with enough CPU capacity,
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regardless of their nice values;
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c. since there is spare capacity all tasks must be blocking/sleeping
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regularly and balancing at wake-up is sufficient.
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As soon as one CPU goes above the 80% tipping point, at least one of the three
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assumptions above becomes incorrect. In this scenario, the 'overutilized' flag
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is raised for the entire root domain, EAS is disabled, and the load-balancer is
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re-enabled. By doing so, the scheduler falls back onto load-based algorithms for
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wake-up and load balance under CPU-bound conditions. This provides a better
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respect of the nice values of tasks.
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Since the notion of overutilization largely relies on detecting whether or not
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there is some idle time in the system, the CPU capacity 'stolen' by higher
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(than CFS) scheduling classes (as well as IRQ) must be taken into account. As
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such, the detection of overutilization accounts for the capacity used not only
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by CFS tasks, but also by the other scheduling classes and IRQ.
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6. Dependencies and requirements for EAS
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----------------------------------------
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Energy Aware Scheduling depends on the CPUs of the system having specific
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hardware properties and on other features of the kernel being enabled. This
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section lists these dependencies and provides hints as to how they can be met.
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6.1 - Asymmetric CPU topology
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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As mentioned in the introduction, EAS is only supported on platforms with
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asymmetric CPU topologies for now. This requirement is checked at run-time by
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looking for the presence of the SD_ASYM_CPUCAPACITY flag when the scheduling
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domains are built.
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The flag is set/cleared automatically by the scheduler topology code whenever
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there are CPUs with different capacities in a root domain. The capacities of
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CPUs are provided by arch-specific code through the arch_scale_cpu_capacity()
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callback. As an example, arm and arm64 share an implementation of this callback
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which uses a combination of CPUFreq data and device-tree bindings to compute the
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capacity of CPUs (see drivers/base/arch_topology.c for more details).
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So, in order to use EAS on your platform your architecture must implement the
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arch_scale_cpu_capacity() callback, and some of the CPUs must have a lower
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capacity than others.
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Please note that EAS is not fundamentally incompatible with SMP, but no
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significant savings on SMP platforms have been observed yet. This restriction
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could be amended in the future if proven otherwise.
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6.2 - Energy Model presence
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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EAS uses the EM of a platform to estimate the impact of scheduling decisions on
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energy. So, your platform must provide power cost tables to the EM framework in
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order to make EAS start. To do so, please refer to documentation of the
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independent EM framework in Documentation/power/energy-model.rst.
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Please also note that the scheduling domains need to be re-built after the
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EM has been registered in order to start EAS.
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6.3 - Energy Model complexity
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The task wake-up path is very latency-sensitive. When the EM of a platform is
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too complex (too many CPUs, too many performance domains, too many performance
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states, ...), the cost of using it in the wake-up path can become prohibitive.
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The energy-aware wake-up algorithm has a complexity of:
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C = Nd * (Nc + Ns)
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with: Nd the number of performance domains; Nc the number of CPUs; and Ns the
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total number of OPPs (ex: for two perf. domains with 4 OPPs each, Ns = 8).
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A complexity check is performed at the root domain level, when scheduling
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domains are built. EAS will not start on a root domain if its C happens to be
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higher than the completely arbitrary EM_MAX_COMPLEXITY threshold (2048 at the
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time of writing).
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If you really want to use EAS but the complexity of your platform's Energy
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Model is too high to be used with a single root domain, you're left with only
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two possible options:
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1. split your system into separate, smaller, root domains using exclusive
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cpusets and enable EAS locally on each of them. This option has the
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benefit to work out of the box but the drawback of preventing load
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balance between root domains, which can result in an unbalanced system
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overall;
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2. submit patches to reduce the complexity of the EAS wake-up algorithm,
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hence enabling it to cope with larger EMs in reasonable time.
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6.4 - Schedutil governor
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^^^^^^^^^^^^^^^^^^^^^^^^
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EAS tries to predict at which OPP will the CPUs be running in the close future
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|
in order to estimate their energy consumption. To do so, it is assumed that OPPs
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of CPUs follow their utilization.
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|
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|
Although it is very difficult to provide hard guarantees regarding the accuracy
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|
of this assumption in practice (because the hardware might not do what it is
|
|
told to do, for example), schedutil as opposed to other CPUFreq governors at
|
|
least _requests_ frequencies calculated using the utilization signals.
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Consequently, the only sane governor to use together with EAS is schedutil,
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|
because it is the only one providing some degree of consistency between
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frequency requests and energy predictions.
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Using EAS with any other governor than schedutil is not supported.
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6.5 Scale-invariant utilization signals
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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|
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|
In order to make accurate prediction across CPUs and for all performance
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states, EAS needs frequency-invariant and CPU-invariant PELT signals. These can
|
|
be obtained using the architecture-defined arch_scale{cpu,freq}_capacity()
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|
callbacks.
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|
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Using EAS on a platform that doesn't implement these two callbacks is not
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|
supported.
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|
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6.6 Multithreading (SMT)
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^^^^^^^^^^^^^^^^^^^^^^^^
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|
EAS in its current form is SMT unaware and is not able to leverage
|
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multithreaded hardware to save energy. EAS considers threads as independent
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|
CPUs, which can actually be counter-productive for both performance and energy.
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|
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|
EAS on SMT is not supported.
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