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The AD5681R/AD5682R/AD5683/AD5683R are a family of one channel DACs with 12-bit, 14-bit and 16-bit precision respectively. The devices have either no built-in reference, or built-in 2.5V reference. These devices are similar to AD5691R/AD5692R/AD5693/AD5693R except with a few notable differences: * they use the SPI interface instead of I2C * in the write control register, DB18 and DB17 are used for setting the power mode, while DB16 is the REF bit. This is why a new regmap type was defined and checked accordingly. * the shift register is 24 bits wide, the first four bits are the command bits followed by the data bits. As the data comprises of 20-bit, 18-bit or 16-bit input code, this means that 4 LSB bits are don't care. This is why the data needs to be shifted on the left with four bits. Therefore, AD5683_REGMAP is checked inside a switch case in the ad5686_spi_write() function. On the other hand, similar devices such as AD5693R family, have the 4 MSB command bits followed by 4 don't care bits. Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/AD5683R_5682R_5681R_5683.pdf Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* This file is part of AD5686 DAC driver
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*
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* Copyright 2018 Analog Devices Inc.
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*/
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#ifndef __DRIVERS_IIO_DAC_AD5686_H__
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#define __DRIVERS_IIO_DAC_AD5686_H__
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#include <linux/types.h>
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#include <linux/cache.h>
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#include <linux/mutex.h>
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#include <linux/kernel.h>
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#define AD5683_DATA(x) ((x) << 4)
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#define AD5686_ADDR(x) ((x) << 16)
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#define AD5686_CMD(x) ((x) << 20)
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#define AD5686_ADDR_DAC(chan) (0x1 << (chan))
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#define AD5686_ADDR_ALL_DAC 0xF
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#define AD5686_CMD_NOOP 0x0
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#define AD5686_CMD_WRITE_INPUT_N 0x1
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#define AD5686_CMD_UPDATE_DAC_N 0x2
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#define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3
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#define AD5686_CMD_POWERDOWN_DAC 0x4
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#define AD5686_CMD_LDAC_MASK 0x5
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#define AD5686_CMD_RESET 0x6
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#define AD5686_CMD_INTERNAL_REFER_SETUP 0x7
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#define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8
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#define AD5686_CMD_READBACK_ENABLE 0x9
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#define AD5686_LDAC_PWRDN_NONE 0x0
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#define AD5686_LDAC_PWRDN_1K 0x1
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#define AD5686_LDAC_PWRDN_100K 0x2
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#define AD5686_LDAC_PWRDN_3STATE 0x3
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#define AD5686_CMD_CONTROL_REG 0x4
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#define AD5686_CMD_READBACK_ENABLE_V2 0x5
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#define AD5683_REF_BIT_MSK BIT(12)
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#define AD5693_REF_BIT_MSK BIT(12)
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/**
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* ad5686_supported_device_ids:
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*/
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enum ad5686_supported_device_ids {
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ID_AD5671R,
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ID_AD5672R,
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ID_AD5675R,
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ID_AD5676,
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ID_AD5676R,
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ID_AD5681R,
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ID_AD5682R,
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ID_AD5683,
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ID_AD5683R,
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ID_AD5684,
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ID_AD5684R,
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ID_AD5685R,
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ID_AD5686,
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ID_AD5686R,
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ID_AD5691R,
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ID_AD5692R,
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ID_AD5693,
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ID_AD5693R,
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ID_AD5694,
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ID_AD5694R,
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ID_AD5695R,
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ID_AD5696,
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ID_AD5696R,
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};
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enum ad5686_regmap_type {
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AD5683_REGMAP,
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AD5686_REGMAP,
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AD5693_REGMAP
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};
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struct ad5686_state;
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typedef int (*ad5686_write_func)(struct ad5686_state *st,
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u8 cmd, u8 addr, u16 val);
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typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr);
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/**
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* struct ad5686_chip_info - chip specific information
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* @int_vref_mv: AD5620/40/60: the internal reference voltage
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* @num_channels: number of channels
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* @channel: channel specification
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* @regmap_type: register map layout variant
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*/
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struct ad5686_chip_info {
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u16 int_vref_mv;
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unsigned int num_channels;
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struct iio_chan_spec *channels;
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enum ad5686_regmap_type regmap_type;
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};
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/**
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* struct ad5446_state - driver instance specific data
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* @spi: spi_device
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* @chip_info: chip model specific constants, available modes etc
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* @reg: supply regulator
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* @vref_mv: actual reference voltage used
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* @pwr_down_mask: power down mask
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* @pwr_down_mode: current power down mode
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* @use_internal_vref: set to true if the internal reference voltage is used
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* @data: spi transfer buffers
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*/
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struct ad5686_state {
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struct device *dev;
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const struct ad5686_chip_info *chip_info;
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struct regulator *reg;
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unsigned short vref_mv;
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unsigned int pwr_down_mask;
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unsigned int pwr_down_mode;
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ad5686_write_func write;
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ad5686_read_func read;
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bool use_internal_vref;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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__be32 d32;
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__be16 d16;
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u8 d8[4];
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} data[3] ____cacheline_aligned;
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};
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int ad5686_probe(struct device *dev,
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enum ad5686_supported_device_ids chip_type,
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const char *name, ad5686_write_func write,
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ad5686_read_func read);
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int ad5686_remove(struct device *dev);
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#endif /* __DRIVERS_IIO_DAC_AD5686_H__ */
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