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POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named Processor Stop Status and Control Register (PSSCR) is added which controls the behavior of stop instruction. PSSCR layout: ---------------------------------------------------------- | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | ---------------------------------------------------------- 0 4 41 42 43 44 48 54 56 60 PSSCR key fields: Bits 0:3 - Power-Saving Level Status. This field indicates the lowest power-saving state the thread entered since stop instruction was last executed. Bit 42 - Enable State Loss 0 - No state is lost irrespective of other fields 1 - Allows state loss Bits 44:47 - Power-Saving Level Limit This limits the power-saving level that can be entered into. Bits 60:63 - Requested Level Used to specify which power-saving level must be entered on executing stop instruction This patch adds support for stop instruction and PSSCR handling. Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
23 lines
572 B
C
23 lines
572 B
C
#ifndef _ASM_POWERPC_CPUIDLE_H
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#define _ASM_POWERPC_CPUIDLE_H
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#ifdef CONFIG_PPC_POWERNV
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/* Used in powernv idle state management */
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#define PNV_THREAD_RUNNING 0
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#define PNV_THREAD_NAP 1
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#define PNV_THREAD_SLEEP 2
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#define PNV_THREAD_WINKLE 3
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#define PNV_CORE_IDLE_LOCK_BIT 0x100
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#define PNV_CORE_IDLE_THREAD_BITS 0x0FF
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#ifndef __ASSEMBLY__
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extern u32 pnv_fastsleep_workaround_at_entry[];
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extern u32 pnv_fastsleep_workaround_at_exit[];
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extern u64 pnv_first_deep_stop_state;
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#endif
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#endif
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#endif
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