mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
dc0b1aa3e2
This adds pin configuration support for the U300 driver pair, we can now read out the biasing and drive mode in debugfs and configure it using the new configuration API. ChangeLog v1->v2: - Migrate to pin config and generic pin config changes. ChangeLog v2->v3: - Adjust to generic pin config changes in v7 patch set. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
90 lines
1.6 KiB
Plaintext
90 lines
1.6 KiB
Plaintext
#
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# PINCTRL infrastructure and drivers
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#
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config PINCTRL
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bool
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depends on EXPERIMENTAL
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if PINCTRL
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menu "Pin controllers"
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depends on PINCTRL
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config PINMUX
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bool "Support pin multiplexing controllers"
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config PINCONF
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bool "Support pin configuration controllers"
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config GENERIC_PINCONF
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bool
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select PINCONF
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config DEBUG_PINCTRL
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bool "Debug PINCTRL calls"
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depends on DEBUG_KERNEL
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help
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Say Y here to add some extra checks and diagnostics to PINCTRL calls.
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config PINCTRL_PXA3xx
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bool
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select PINMUX
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config PINCTRL_MMP2
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bool "MMP2 pin controller driver"
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depends on ARCH_MMP
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select PINCTRL_PXA3xx
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select PINCONF
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config PINCTRL_PXA168
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bool "PXA168 pin controller driver"
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depends on ARCH_MMP
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select PINCTRL_PXA3xx
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select PINCONF
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config PINCTRL_PXA910
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bool "PXA910 pin controller driver"
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depends on ARCH_MMP
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select PINCTRL_PXA3xx
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select PINCONF
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config PINCTRL_SIRF
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bool "CSR SiRFprimaII pin controller driver"
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depends on ARCH_PRIMA2
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select PINMUX
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config PINCTRL_TEGRA
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bool
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config PINCTRL_TEGRA20
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bool
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select PINMUX
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select PINCONF
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select PINCTRL_TEGRA
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config PINCTRL_TEGRA30
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bool
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select PINMUX
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select PINCONF
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select PINCTRL_TEGRA
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config PINCTRL_U300
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bool "U300 pin controller driver"
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depends on ARCH_U300
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select PINMUX
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select GENERIC_PINCONF
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config PINCTRL_COH901
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bool "ST-Ericsson U300 COH 901 335/571 GPIO"
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depends on GPIOLIB && ARCH_U300 && PINMUX_U300
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help
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Say yes here to support GPIO interface on ST-Ericsson U300.
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The names of the two IP block variants supported are
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COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
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ports of 8 GPIO pins each.
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endmenu
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endif
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