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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d35ade8ff7
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, so the sdhci_pltfm_data structure can be const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
257 lines
6.6 KiB
C
257 lines
6.6 KiB
C
/*
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* Support of SDHCI platform devices for Microchip PIC32.
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*
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* Copyright (C) 2015 Microchip
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* Andrei Pistirica, Paul Thacker
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*
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* Inspired by sdhci-pltfm.c
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/mmc/host.h>
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#include <linux/io.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#include <linux/platform_data/sdhci-pic32.h>
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#define SDH_SHARED_BUS_CTRL 0x000000E0
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#define SDH_SHARED_BUS_NR_CLK_PINS_MASK 0x7
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#define SDH_SHARED_BUS_NR_IRQ_PINS_MASK 0x30
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#define SDH_SHARED_BUS_CLK_PINS 0x10
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#define SDH_SHARED_BUS_IRQ_PINS 0x14
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#define SDH_CAPS_SDH_SLOT_TYPE_MASK 0xC0000000
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#define SDH_SLOT_TYPE_REMOVABLE 0x0
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#define SDH_SLOT_TYPE_EMBEDDED 0x1
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#define SDH_SLOT_TYPE_SHARED_BUS 0x2
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#define SDHCI_CTRL_CDSSEL 0x80
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#define SDHCI_CTRL_CDTLVL 0x40
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#define ADMA_FIFO_RD_THSHLD 512
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#define ADMA_FIFO_WR_THSHLD 512
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struct pic32_sdhci_priv {
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struct platform_device *pdev;
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struct clk *sys_clk;
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struct clk *base_clk;
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};
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static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host)
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{
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struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
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return clk_get_rate(sdhci_pdata->base_clk);
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}
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static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width)
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{
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u8 ctrl;
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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if (width == MMC_BUS_WIDTH_8) {
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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if (host->version >= SDHCI_SPEC_300)
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ctrl |= SDHCI_CTRL_8BITBUS;
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} else {
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if (host->version >= SDHCI_SPEC_300)
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ctrl &= ~SDHCI_CTRL_8BITBUS;
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if (width == MMC_BUS_WIDTH_4)
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ctrl |= SDHCI_CTRL_4BITBUS;
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else
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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}
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/* CD select and test bits must be set for errata workaround. */
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ctrl &= ~SDHCI_CTRL_CDTLVL;
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ctrl |= SDHCI_CTRL_CDSSEL;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host)
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{
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/*
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* The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we
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* can't depend on its value in any way.
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*/
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return 0;
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}
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static const struct sdhci_ops pic32_sdhci_ops = {
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.get_max_clock = pic32_sdhci_get_max_clock,
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.set_clock = sdhci_set_clock,
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.set_bus_width = pic32_sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.get_ro = pic32_sdhci_get_ro,
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};
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static const struct sdhci_pltfm_data sdhci_pic32_pdata = {
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.ops = &pic32_sdhci_ops,
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.quirks = SDHCI_QUIRK_NO_HISPD_BIT,
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.quirks2 = SDHCI_QUIRK2_NO_1_8_V,
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};
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static void pic32_sdhci_shared_bus(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL);
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u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
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u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
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/* select first clock */
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if (clk_pins & 1)
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bus |= (1 << SDH_SHARED_BUS_CLK_PINS);
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/* select first interrupt */
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if (irq_pins & 1)
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bus |= (1 << SDH_SHARED_BUS_IRQ_PINS);
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writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
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}
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static int pic32_sdhci_probe_platform(struct platform_device *pdev,
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struct pic32_sdhci_priv *pdata)
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{
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int ret = 0;
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u32 caps_slot_type;
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struct sdhci_host *host = platform_get_drvdata(pdev);
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/* Check card slot connected on shared bus. */
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host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
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caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30;
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if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS)
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pic32_sdhci_shared_bus(pdev);
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return ret;
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}
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static int pic32_sdhci_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct pic32_sdhci_priv *sdhci_pdata;
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struct pic32_sdhci_platform_data *plat_data;
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int ret;
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host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata,
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sizeof(struct pic32_sdhci_priv));
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if (IS_ERR(host)) {
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ret = PTR_ERR(host);
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goto err;
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}
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pltfm_host = sdhci_priv(host);
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sdhci_pdata = sdhci_pltfm_priv(pltfm_host);
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plat_data = pdev->dev.platform_data;
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if (plat_data && plat_data->setup_dma) {
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ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD,
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ADMA_FIFO_WR_THSHLD);
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if (ret)
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goto err_host;
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}
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sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
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if (IS_ERR(sdhci_pdata->sys_clk)) {
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ret = PTR_ERR(sdhci_pdata->sys_clk);
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dev_err(&pdev->dev, "Error getting clock\n");
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goto err_host;
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}
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ret = clk_prepare_enable(sdhci_pdata->sys_clk);
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if (ret) {
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dev_err(&pdev->dev, "Error enabling clock\n");
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goto err_host;
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}
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sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk");
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if (IS_ERR(sdhci_pdata->base_clk)) {
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ret = PTR_ERR(sdhci_pdata->base_clk);
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dev_err(&pdev->dev, "Error getting clock\n");
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goto err_sys_clk;
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}
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ret = clk_prepare_enable(sdhci_pdata->base_clk);
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if (ret) {
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dev_err(&pdev->dev, "Error enabling clock\n");
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goto err_base_clk;
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}
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err_base_clk;
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ret = pic32_sdhci_probe_platform(pdev, sdhci_pdata);
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if (ret) {
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dev_err(&pdev->dev, "failed to probe platform!\n");
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goto err_base_clk;
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}
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ret = sdhci_add_host(host);
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if (ret) {
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dev_err(&pdev->dev, "error adding host\n");
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goto err_base_clk;
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}
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dev_info(&pdev->dev, "Successfully added sdhci host\n");
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return 0;
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err_base_clk:
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clk_disable_unprepare(sdhci_pdata->base_clk);
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err_sys_clk:
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clk_disable_unprepare(sdhci_pdata->sys_clk);
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err_host:
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sdhci_pltfm_free(pdev);
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err:
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dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret);
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return ret;
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}
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static int pic32_sdhci_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
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u32 scratch;
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scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
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sdhci_remove_host(host, scratch == (u32)~0);
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clk_disable_unprepare(sdhci_pdata->base_clk);
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clk_disable_unprepare(sdhci_pdata->sys_clk);
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sdhci_pltfm_free(pdev);
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return 0;
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}
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static const struct of_device_id pic32_sdhci_id_table[] = {
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{ .compatible = "microchip,pic32mzda-sdhci" },
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{}
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};
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MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table);
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static struct platform_driver pic32_sdhci_driver = {
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.driver = {
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.name = "pic32-sdhci",
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.of_match_table = of_match_ptr(pic32_sdhci_id_table),
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},
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.probe = pic32_sdhci_probe,
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.remove = pic32_sdhci_remove,
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};
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module_platform_driver(pic32_sdhci_driver);
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MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver");
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MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker");
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MODULE_LICENSE("GPL v2");
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