mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 18:36:41 +07:00
5be4d4c94b
Modify crypto drivers to use the generic SG helper since both of them are equivalent and the one from crypto is redundant. See also:468577abe3
reverted inb2ab4a57b0
Signed-off-by: Cristian Stoica <cristian.stoica@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
800 lines
22 KiB
C
800 lines
22 KiB
C
/**
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* Routines supporting the Power 7+ Nest Accelerators driver
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*
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* Copyright (C) 2011-2012 International Business Machines Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 only.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Author: Kent Yoder <yoder1@us.ibm.com>
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*/
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#include <crypto/internal/hash.h>
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#include <crypto/hash.h>
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include <crypto/algapi.h>
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#include <crypto/scatterwalk.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/crypto.h>
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#include <linux/scatterlist.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <asm/hvcall.h>
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#include <asm/vio.h>
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#include "nx_csbcpb.h"
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#include "nx.h"
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/**
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* nx_hcall_sync - make an H_COP_OP hcall for the passed in op structure
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*
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* @nx_ctx: the crypto context handle
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* @op: PFO operation struct to pass in
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* @may_sleep: flag indicating the request can sleep
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*
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* Make the hcall, retrying while the hardware is busy. If we cannot yield
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* the thread, limit the number of retries to 10 here.
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*/
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int nx_hcall_sync(struct nx_crypto_ctx *nx_ctx,
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struct vio_pfo_op *op,
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u32 may_sleep)
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{
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int rc, retries = 10;
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struct vio_dev *viodev = nx_driver.viodev;
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atomic_inc(&(nx_ctx->stats->sync_ops));
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do {
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rc = vio_h_cop_sync(viodev, op);
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} while (rc == -EBUSY && !may_sleep && retries--);
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if (rc) {
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dev_dbg(&viodev->dev, "vio_h_cop_sync failed: rc: %d "
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"hcall rc: %ld\n", rc, op->hcall_err);
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atomic_inc(&(nx_ctx->stats->errors));
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atomic_set(&(nx_ctx->stats->last_error), op->hcall_err);
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atomic_set(&(nx_ctx->stats->last_error_pid), current->pid);
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}
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return rc;
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}
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/**
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* nx_build_sg_list - build an NX scatter list describing a single buffer
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*
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* @sg_head: pointer to the first scatter list element to build
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* @start_addr: pointer to the linear buffer
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* @len: length of the data at @start_addr
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* @sgmax: the largest number of scatter list elements we're allowed to create
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*
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* This function will start writing nx_sg elements at @sg_head and keep
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* writing them until all of the data from @start_addr is described or
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* until sgmax elements have been written. Scatter list elements will be
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* created such that none of the elements describes a buffer that crosses a 4K
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* boundary.
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*/
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struct nx_sg *nx_build_sg_list(struct nx_sg *sg_head,
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u8 *start_addr,
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unsigned int *len,
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u32 sgmax)
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{
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unsigned int sg_len = 0;
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struct nx_sg *sg;
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u64 sg_addr = (u64)start_addr;
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u64 end_addr;
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/* determine the start and end for this address range - slightly
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* different if this is in VMALLOC_REGION */
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if (is_vmalloc_addr(start_addr))
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sg_addr = page_to_phys(vmalloc_to_page(start_addr))
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+ offset_in_page(sg_addr);
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else
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sg_addr = __pa(sg_addr);
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end_addr = sg_addr + *len;
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/* each iteration will write one struct nx_sg element and add the
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* length of data described by that element to sg_len. Once @len bytes
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* have been described (or @sgmax elements have been written), the
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* loop ends. min_t is used to ensure @end_addr falls on the same page
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* as sg_addr, if not, we need to create another nx_sg element for the
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* data on the next page.
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*
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* Also when using vmalloc'ed data, every time that a system page
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* boundary is crossed the physical address needs to be re-calculated.
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*/
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for (sg = sg_head; sg_len < *len; sg++) {
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u64 next_page;
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sg->addr = sg_addr;
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sg_addr = min_t(u64, NX_PAGE_NUM(sg_addr + NX_PAGE_SIZE),
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end_addr);
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next_page = (sg->addr & PAGE_MASK) + PAGE_SIZE;
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sg->len = min_t(u64, sg_addr, next_page) - sg->addr;
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sg_len += sg->len;
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if (sg_addr >= next_page &&
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is_vmalloc_addr(start_addr + sg_len)) {
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sg_addr = page_to_phys(vmalloc_to_page(
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start_addr + sg_len));
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end_addr = sg_addr + *len - sg_len;
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}
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if ((sg - sg_head) == sgmax) {
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pr_err("nx: scatter/gather list overflow, pid: %d\n",
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current->pid);
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sg++;
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break;
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}
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}
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*len = sg_len;
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/* return the moved sg_head pointer */
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return sg;
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}
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/**
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* nx_walk_and_build - walk a linux scatterlist and build an nx scatterlist
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*
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* @nx_dst: pointer to the first nx_sg element to write
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* @sglen: max number of nx_sg entries we're allowed to write
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* @sg_src: pointer to the source linux scatterlist to walk
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* @start: number of bytes to fast-forward past at the beginning of @sg_src
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* @src_len: number of bytes to walk in @sg_src
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*/
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struct nx_sg *nx_walk_and_build(struct nx_sg *nx_dst,
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unsigned int sglen,
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struct scatterlist *sg_src,
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unsigned int start,
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unsigned int *src_len)
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{
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struct scatter_walk walk;
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struct nx_sg *nx_sg = nx_dst;
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unsigned int n, offset = 0, len = *src_len;
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char *dst;
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/* we need to fast forward through @start bytes first */
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for (;;) {
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scatterwalk_start(&walk, sg_src);
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if (start < offset + sg_src->length)
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break;
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offset += sg_src->length;
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sg_src = sg_next(sg_src);
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}
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/* start - offset is the number of bytes to advance in the scatterlist
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* element we're currently looking at */
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scatterwalk_advance(&walk, start - offset);
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while (len && (nx_sg - nx_dst) < sglen) {
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n = scatterwalk_clamp(&walk, len);
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if (!n) {
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/* In cases where we have scatterlist chain sg_next
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* handles with it properly */
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scatterwalk_start(&walk, sg_next(walk.sg));
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n = scatterwalk_clamp(&walk, len);
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}
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dst = scatterwalk_map(&walk);
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nx_sg = nx_build_sg_list(nx_sg, dst, &n, sglen - (nx_sg - nx_dst));
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len -= n;
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scatterwalk_unmap(dst);
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scatterwalk_advance(&walk, n);
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scatterwalk_done(&walk, SCATTERWALK_FROM_SG, len);
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}
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/* update to_process */
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*src_len -= len;
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/* return the moved destination pointer */
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return nx_sg;
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}
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/**
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* trim_sg_list - ensures the bound in sg list.
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* @sg: sg list head
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* @end: sg lisg end
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* @delta: is the amount we need to crop in order to bound the list.
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*
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*/
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static long int trim_sg_list(struct nx_sg *sg, struct nx_sg *end, unsigned int delta)
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{
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while (delta && end > sg) {
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struct nx_sg *last = end - 1;
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if (last->len > delta) {
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last->len -= delta;
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delta = 0;
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} else {
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end--;
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delta -= last->len;
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}
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}
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return (sg - end) * sizeof(struct nx_sg);
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}
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/**
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* nx_sha_build_sg_list - walk and build sg list to sha modes
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* using right bounds and limits.
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* @nx_ctx: NX crypto context for the lists we're building
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* @nx_sg: current sg list in or out list
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* @op_len: current op_len to be used in order to build a sg list
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* @nbytes: number or bytes to be processed
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* @offset: buf offset
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* @mode: SHA256 or SHA512
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*/
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int nx_sha_build_sg_list(struct nx_crypto_ctx *nx_ctx,
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struct nx_sg *nx_in_outsg,
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s64 *op_len,
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unsigned int *nbytes,
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u8 *offset,
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u32 mode)
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{
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unsigned int delta = 0;
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unsigned int total = *nbytes;
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struct nx_sg *nx_insg = nx_in_outsg;
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unsigned int max_sg_len;
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max_sg_len = min_t(u64, nx_ctx->ap->sglen,
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nx_driver.of.max_sg_len/sizeof(struct nx_sg));
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max_sg_len = min_t(u64, max_sg_len,
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nx_ctx->ap->databytelen/NX_PAGE_SIZE);
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*nbytes = min_t(u64, *nbytes, nx_ctx->ap->databytelen);
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nx_insg = nx_build_sg_list(nx_insg, offset, nbytes, max_sg_len);
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switch (mode) {
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case NX_DS_SHA256:
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if (*nbytes < total)
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delta = *nbytes - (*nbytes & ~(SHA256_BLOCK_SIZE - 1));
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break;
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case NX_DS_SHA512:
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if (*nbytes < total)
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delta = *nbytes - (*nbytes & ~(SHA512_BLOCK_SIZE - 1));
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break;
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default:
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return -EINVAL;
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}
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*op_len = trim_sg_list(nx_in_outsg, nx_insg, delta);
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return 0;
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}
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/**
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* nx_build_sg_lists - walk the input scatterlists and build arrays of NX
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* scatterlists based on them.
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*
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* @nx_ctx: NX crypto context for the lists we're building
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* @desc: the block cipher descriptor for the operation
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* @dst: destination scatterlist
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* @src: source scatterlist
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* @nbytes: length of data described in the scatterlists
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* @offset: number of bytes to fast-forward past at the beginning of
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* scatterlists.
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* @iv: destination for the iv data, if the algorithm requires it
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*
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* This is common code shared by all the AES algorithms. It uses the block
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* cipher walk routines to traverse input and output scatterlists, building
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* corresponding NX scatterlists
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*/
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int nx_build_sg_lists(struct nx_crypto_ctx *nx_ctx,
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struct blkcipher_desc *desc,
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struct scatterlist *dst,
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struct scatterlist *src,
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unsigned int *nbytes,
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unsigned int offset,
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u8 *iv)
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{
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unsigned int delta = 0;
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unsigned int total = *nbytes;
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struct nx_sg *nx_insg = nx_ctx->in_sg;
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struct nx_sg *nx_outsg = nx_ctx->out_sg;
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unsigned int max_sg_len;
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max_sg_len = min_t(u64, nx_ctx->ap->sglen,
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nx_driver.of.max_sg_len/sizeof(struct nx_sg));
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max_sg_len = min_t(u64, max_sg_len,
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nx_ctx->ap->databytelen/NX_PAGE_SIZE);
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if (iv)
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memcpy(iv, desc->info, AES_BLOCK_SIZE);
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*nbytes = min_t(u64, *nbytes, nx_ctx->ap->databytelen);
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nx_outsg = nx_walk_and_build(nx_outsg, max_sg_len, dst,
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offset, nbytes);
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nx_insg = nx_walk_and_build(nx_insg, max_sg_len, src,
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offset, nbytes);
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if (*nbytes < total)
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delta = *nbytes - (*nbytes & ~(AES_BLOCK_SIZE - 1));
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/* these lengths should be negative, which will indicate to phyp that
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* the input and output parameters are scatterlists, not linear
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* buffers */
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nx_ctx->op.inlen = trim_sg_list(nx_ctx->in_sg, nx_insg, delta);
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nx_ctx->op.outlen = trim_sg_list(nx_ctx->out_sg, nx_outsg, delta);
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return 0;
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}
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/**
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* nx_ctx_init - initialize an nx_ctx's vio_pfo_op struct
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*
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* @nx_ctx: the nx context to initialize
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* @function: the function code for the op
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*/
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void nx_ctx_init(struct nx_crypto_ctx *nx_ctx, unsigned int function)
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{
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spin_lock_init(&nx_ctx->lock);
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memset(nx_ctx->kmem, 0, nx_ctx->kmem_len);
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nx_ctx->csbcpb->csb.valid |= NX_CSB_VALID_BIT;
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nx_ctx->op.flags = function;
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nx_ctx->op.csbcpb = __pa(nx_ctx->csbcpb);
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nx_ctx->op.in = __pa(nx_ctx->in_sg);
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nx_ctx->op.out = __pa(nx_ctx->out_sg);
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if (nx_ctx->csbcpb_aead) {
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nx_ctx->csbcpb_aead->csb.valid |= NX_CSB_VALID_BIT;
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nx_ctx->op_aead.flags = function;
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nx_ctx->op_aead.csbcpb = __pa(nx_ctx->csbcpb_aead);
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nx_ctx->op_aead.in = __pa(nx_ctx->in_sg);
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nx_ctx->op_aead.out = __pa(nx_ctx->out_sg);
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}
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}
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static void nx_of_update_status(struct device *dev,
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struct property *p,
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struct nx_of *props)
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{
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if (!strncmp(p->value, "okay", p->length)) {
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props->status = NX_WAITING;
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props->flags |= NX_OF_FLAG_STATUS_SET;
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} else {
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dev_info(dev, "%s: status '%s' is not 'okay'\n", __func__,
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(char *)p->value);
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}
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}
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static void nx_of_update_sglen(struct device *dev,
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struct property *p,
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struct nx_of *props)
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{
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if (p->length != sizeof(props->max_sg_len)) {
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dev_err(dev, "%s: unexpected format for "
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"ibm,max-sg-len property\n", __func__);
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dev_dbg(dev, "%s: ibm,max-sg-len is %d bytes "
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"long, expected %zd bytes\n", __func__,
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p->length, sizeof(props->max_sg_len));
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return;
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}
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props->max_sg_len = *(u32 *)p->value;
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props->flags |= NX_OF_FLAG_MAXSGLEN_SET;
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}
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static void nx_of_update_msc(struct device *dev,
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struct property *p,
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struct nx_of *props)
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{
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struct msc_triplet *trip;
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struct max_sync_cop *msc;
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unsigned int bytes_so_far, i, lenp;
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msc = (struct max_sync_cop *)p->value;
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lenp = p->length;
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/* You can't tell if the data read in for this property is sane by its
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* size alone. This is because there are sizes embedded in the data
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* structure. The best we can do is check lengths as we parse and bail
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* as soon as a length error is detected. */
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bytes_so_far = 0;
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while ((bytes_so_far + sizeof(struct max_sync_cop)) <= lenp) {
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bytes_so_far += sizeof(struct max_sync_cop);
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trip = msc->trip;
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for (i = 0;
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((bytes_so_far + sizeof(struct msc_triplet)) <= lenp) &&
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i < msc->triplets;
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i++) {
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if (msc->fc > NX_MAX_FC || msc->mode > NX_MAX_MODE) {
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dev_err(dev, "unknown function code/mode "
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"combo: %d/%d (ignored)\n", msc->fc,
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msc->mode);
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goto next_loop;
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}
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switch (trip->keybitlen) {
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case 128:
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case 160:
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props->ap[msc->fc][msc->mode][0].databytelen =
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trip->databytelen;
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props->ap[msc->fc][msc->mode][0].sglen =
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trip->sglen;
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break;
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case 192:
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props->ap[msc->fc][msc->mode][1].databytelen =
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trip->databytelen;
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props->ap[msc->fc][msc->mode][1].sglen =
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trip->sglen;
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break;
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case 256:
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if (msc->fc == NX_FC_AES) {
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props->ap[msc->fc][msc->mode][2].
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databytelen = trip->databytelen;
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props->ap[msc->fc][msc->mode][2].sglen =
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trip->sglen;
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} else if (msc->fc == NX_FC_AES_HMAC ||
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msc->fc == NX_FC_SHA) {
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props->ap[msc->fc][msc->mode][1].
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databytelen = trip->databytelen;
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props->ap[msc->fc][msc->mode][1].sglen =
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trip->sglen;
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} else {
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dev_warn(dev, "unknown function "
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"code/key bit len combo"
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": (%u/256)\n", msc->fc);
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}
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break;
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case 512:
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props->ap[msc->fc][msc->mode][2].databytelen =
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trip->databytelen;
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props->ap[msc->fc][msc->mode][2].sglen =
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trip->sglen;
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break;
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default:
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dev_warn(dev, "unknown function code/key bit "
|
|
"len combo: (%u/%u)\n", msc->fc,
|
|
trip->keybitlen);
|
|
break;
|
|
}
|
|
next_loop:
|
|
bytes_so_far += sizeof(struct msc_triplet);
|
|
trip++;
|
|
}
|
|
|
|
msc = (struct max_sync_cop *)trip;
|
|
}
|
|
|
|
props->flags |= NX_OF_FLAG_MAXSYNCCOP_SET;
|
|
}
|
|
|
|
/**
|
|
* nx_of_init - read openFirmware values from the device tree
|
|
*
|
|
* @dev: device handle
|
|
* @props: pointer to struct to hold the properties values
|
|
*
|
|
* Called once at driver probe time, this function will read out the
|
|
* openFirmware properties we use at runtime. If all the OF properties are
|
|
* acceptable, when we exit this function props->flags will indicate that
|
|
* we're ready to register our crypto algorithms.
|
|
*/
|
|
static void nx_of_init(struct device *dev, struct nx_of *props)
|
|
{
|
|
struct device_node *base_node = dev->of_node;
|
|
struct property *p;
|
|
|
|
p = of_find_property(base_node, "status", NULL);
|
|
if (!p)
|
|
dev_info(dev, "%s: property 'status' not found\n", __func__);
|
|
else
|
|
nx_of_update_status(dev, p, props);
|
|
|
|
p = of_find_property(base_node, "ibm,max-sg-len", NULL);
|
|
if (!p)
|
|
dev_info(dev, "%s: property 'ibm,max-sg-len' not found\n",
|
|
__func__);
|
|
else
|
|
nx_of_update_sglen(dev, p, props);
|
|
|
|
p = of_find_property(base_node, "ibm,max-sync-cop", NULL);
|
|
if (!p)
|
|
dev_info(dev, "%s: property 'ibm,max-sync-cop' not found\n",
|
|
__func__);
|
|
else
|
|
nx_of_update_msc(dev, p, props);
|
|
}
|
|
|
|
/**
|
|
* nx_register_algs - register algorithms with the crypto API
|
|
*
|
|
* Called from nx_probe()
|
|
*
|
|
* If all OF properties are in an acceptable state, the driver flags will
|
|
* indicate that we're ready and we'll create our debugfs files and register
|
|
* out crypto algorithms.
|
|
*/
|
|
static int nx_register_algs(void)
|
|
{
|
|
int rc = -1;
|
|
|
|
if (nx_driver.of.flags != NX_OF_FLAG_MASK_READY)
|
|
goto out;
|
|
|
|
memset(&nx_driver.stats, 0, sizeof(struct nx_stats));
|
|
|
|
rc = NX_DEBUGFS_INIT(&nx_driver);
|
|
if (rc)
|
|
goto out;
|
|
|
|
nx_driver.of.status = NX_OKAY;
|
|
|
|
rc = crypto_register_alg(&nx_ecb_aes_alg);
|
|
if (rc)
|
|
goto out;
|
|
|
|
rc = crypto_register_alg(&nx_cbc_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_ecb;
|
|
|
|
rc = crypto_register_alg(&nx_ctr_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_cbc;
|
|
|
|
rc = crypto_register_alg(&nx_ctr3686_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_ctr;
|
|
|
|
rc = crypto_register_alg(&nx_gcm_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_ctr3686;
|
|
|
|
rc = crypto_register_alg(&nx_gcm4106_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_gcm;
|
|
|
|
rc = crypto_register_alg(&nx_ccm_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_gcm4106;
|
|
|
|
rc = crypto_register_alg(&nx_ccm4309_aes_alg);
|
|
if (rc)
|
|
goto out_unreg_ccm;
|
|
|
|
rc = crypto_register_shash(&nx_shash_sha256_alg);
|
|
if (rc)
|
|
goto out_unreg_ccm4309;
|
|
|
|
rc = crypto_register_shash(&nx_shash_sha512_alg);
|
|
if (rc)
|
|
goto out_unreg_s256;
|
|
|
|
rc = crypto_register_shash(&nx_shash_aes_xcbc_alg);
|
|
if (rc)
|
|
goto out_unreg_s512;
|
|
|
|
goto out;
|
|
|
|
out_unreg_s512:
|
|
crypto_unregister_shash(&nx_shash_sha512_alg);
|
|
out_unreg_s256:
|
|
crypto_unregister_shash(&nx_shash_sha256_alg);
|
|
out_unreg_ccm4309:
|
|
crypto_unregister_alg(&nx_ccm4309_aes_alg);
|
|
out_unreg_ccm:
|
|
crypto_unregister_alg(&nx_ccm_aes_alg);
|
|
out_unreg_gcm4106:
|
|
crypto_unregister_alg(&nx_gcm4106_aes_alg);
|
|
out_unreg_gcm:
|
|
crypto_unregister_alg(&nx_gcm_aes_alg);
|
|
out_unreg_ctr3686:
|
|
crypto_unregister_alg(&nx_ctr3686_aes_alg);
|
|
out_unreg_ctr:
|
|
crypto_unregister_alg(&nx_ctr_aes_alg);
|
|
out_unreg_cbc:
|
|
crypto_unregister_alg(&nx_cbc_aes_alg);
|
|
out_unreg_ecb:
|
|
crypto_unregister_alg(&nx_ecb_aes_alg);
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* nx_crypto_ctx_init - create and initialize a crypto api context
|
|
*
|
|
* @nx_ctx: the crypto api context
|
|
* @fc: function code for the context
|
|
* @mode: the function code specific mode for this context
|
|
*/
|
|
static int nx_crypto_ctx_init(struct nx_crypto_ctx *nx_ctx, u32 fc, u32 mode)
|
|
{
|
|
if (nx_driver.of.status != NX_OKAY) {
|
|
pr_err("Attempt to initialize NX crypto context while device "
|
|
"is not available!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* we need an extra page for csbcpb_aead for these modes */
|
|
if (mode == NX_MODE_AES_GCM || mode == NX_MODE_AES_CCM)
|
|
nx_ctx->kmem_len = (5 * NX_PAGE_SIZE) +
|
|
sizeof(struct nx_csbcpb);
|
|
else
|
|
nx_ctx->kmem_len = (4 * NX_PAGE_SIZE) +
|
|
sizeof(struct nx_csbcpb);
|
|
|
|
nx_ctx->kmem = kmalloc(nx_ctx->kmem_len, GFP_KERNEL);
|
|
if (!nx_ctx->kmem)
|
|
return -ENOMEM;
|
|
|
|
/* the csbcpb and scatterlists must be 4K aligned pages */
|
|
nx_ctx->csbcpb = (struct nx_csbcpb *)(round_up((u64)nx_ctx->kmem,
|
|
(u64)NX_PAGE_SIZE));
|
|
nx_ctx->in_sg = (struct nx_sg *)((u8 *)nx_ctx->csbcpb + NX_PAGE_SIZE);
|
|
nx_ctx->out_sg = (struct nx_sg *)((u8 *)nx_ctx->in_sg + NX_PAGE_SIZE);
|
|
|
|
if (mode == NX_MODE_AES_GCM || mode == NX_MODE_AES_CCM)
|
|
nx_ctx->csbcpb_aead =
|
|
(struct nx_csbcpb *)((u8 *)nx_ctx->out_sg +
|
|
NX_PAGE_SIZE);
|
|
|
|
/* give each context a pointer to global stats and their OF
|
|
* properties */
|
|
nx_ctx->stats = &nx_driver.stats;
|
|
memcpy(nx_ctx->props, nx_driver.of.ap[fc][mode],
|
|
sizeof(struct alg_props) * 3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* entry points from the crypto tfm initializers */
|
|
int nx_crypto_ctx_aes_ccm_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_CCM);
|
|
}
|
|
|
|
int nx_crypto_ctx_aes_gcm_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_GCM);
|
|
}
|
|
|
|
int nx_crypto_ctx_aes_ctr_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_CTR);
|
|
}
|
|
|
|
int nx_crypto_ctx_aes_cbc_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_CBC);
|
|
}
|
|
|
|
int nx_crypto_ctx_aes_ecb_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_ECB);
|
|
}
|
|
|
|
int nx_crypto_ctx_sha_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_SHA, NX_MODE_SHA);
|
|
}
|
|
|
|
int nx_crypto_ctx_aes_xcbc_init(struct crypto_tfm *tfm)
|
|
{
|
|
return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
|
|
NX_MODE_AES_XCBC_MAC);
|
|
}
|
|
|
|
/**
|
|
* nx_crypto_ctx_exit - destroy a crypto api context
|
|
*
|
|
* @tfm: the crypto transform pointer for the context
|
|
*
|
|
* As crypto API contexts are destroyed, this exit hook is called to free the
|
|
* memory associated with it.
|
|
*/
|
|
void nx_crypto_ctx_exit(struct crypto_tfm *tfm)
|
|
{
|
|
struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
|
|
|
|
kzfree(nx_ctx->kmem);
|
|
nx_ctx->csbcpb = NULL;
|
|
nx_ctx->csbcpb_aead = NULL;
|
|
nx_ctx->in_sg = NULL;
|
|
nx_ctx->out_sg = NULL;
|
|
}
|
|
|
|
static int nx_probe(struct vio_dev *viodev, const struct vio_device_id *id)
|
|
{
|
|
dev_dbg(&viodev->dev, "driver probed: %s resource id: 0x%x\n",
|
|
viodev->name, viodev->resource_id);
|
|
|
|
if (nx_driver.viodev) {
|
|
dev_err(&viodev->dev, "%s: Attempt to register more than one "
|
|
"instance of the hardware\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
nx_driver.viodev = viodev;
|
|
|
|
nx_of_init(&viodev->dev, &nx_driver.of);
|
|
|
|
return nx_register_algs();
|
|
}
|
|
|
|
static int nx_remove(struct vio_dev *viodev)
|
|
{
|
|
dev_dbg(&viodev->dev, "entering nx_remove for UA 0x%x\n",
|
|
viodev->unit_address);
|
|
|
|
if (nx_driver.of.status == NX_OKAY) {
|
|
NX_DEBUGFS_FINI(&nx_driver);
|
|
|
|
crypto_unregister_alg(&nx_ccm_aes_alg);
|
|
crypto_unregister_alg(&nx_ccm4309_aes_alg);
|
|
crypto_unregister_alg(&nx_gcm_aes_alg);
|
|
crypto_unregister_alg(&nx_gcm4106_aes_alg);
|
|
crypto_unregister_alg(&nx_ctr_aes_alg);
|
|
crypto_unregister_alg(&nx_ctr3686_aes_alg);
|
|
crypto_unregister_alg(&nx_cbc_aes_alg);
|
|
crypto_unregister_alg(&nx_ecb_aes_alg);
|
|
crypto_unregister_shash(&nx_shash_sha256_alg);
|
|
crypto_unregister_shash(&nx_shash_sha512_alg);
|
|
crypto_unregister_shash(&nx_shash_aes_xcbc_alg);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* module wide initialization/cleanup */
|
|
static int __init nx_init(void)
|
|
{
|
|
return vio_register_driver(&nx_driver.viodriver);
|
|
}
|
|
|
|
static void __exit nx_fini(void)
|
|
{
|
|
vio_unregister_driver(&nx_driver.viodriver);
|
|
}
|
|
|
|
static struct vio_device_id nx_crypto_driver_ids[] = {
|
|
{ "ibm,sym-encryption-v1", "ibm,sym-encryption" },
|
|
{ "", "" }
|
|
};
|
|
MODULE_DEVICE_TABLE(vio, nx_crypto_driver_ids);
|
|
|
|
/* driver state structure */
|
|
struct nx_crypto_driver nx_driver = {
|
|
.viodriver = {
|
|
.id_table = nx_crypto_driver_ids,
|
|
.probe = nx_probe,
|
|
.remove = nx_remove,
|
|
.name = NX_NAME,
|
|
},
|
|
};
|
|
|
|
module_init(nx_init);
|
|
module_exit(nx_fini);
|
|
|
|
MODULE_AUTHOR("Kent Yoder <yoder1@us.ibm.com>");
|
|
MODULE_DESCRIPTION(NX_STRING);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(NX_VERSION);
|