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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.1 KiB
C
100 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* wm8940.h -- WM8940 Soc Audio driver
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*/
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#ifndef _WM8940_H
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#define _WM8940_H
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struct wm8940_setup_data {
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/* Vref to analogue output resistance */
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#define WM8940_VROI_1K 0
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#define WM8940_VROI_30K 1
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unsigned int vroi:1;
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};
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/* WM8940 register space */
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#define WM8940_SOFTRESET 0x00
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#define WM8940_POWER1 0x01
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#define WM8940_POWER2 0x02
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#define WM8940_POWER3 0x03
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#define WM8940_IFACE 0x04
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#define WM8940_COMPANDINGCTL 0x05
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#define WM8940_CLOCK 0x06
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#define WM8940_ADDCNTRL 0x07
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#define WM8940_GPIO 0x08
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#define WM8940_CTLINT 0x09
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#define WM8940_DAC 0x0A
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#define WM8940_DACVOL 0x0B
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#define WM8940_ADC 0x0E
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#define WM8940_ADCVOL 0x0F
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#define WM8940_NOTCH1 0x10
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#define WM8940_NOTCH2 0x11
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#define WM8940_NOTCH3 0x12
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#define WM8940_NOTCH4 0x13
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#define WM8940_NOTCH5 0x14
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#define WM8940_NOTCH6 0x15
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#define WM8940_NOTCH7 0x16
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#define WM8940_NOTCH8 0x17
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#define WM8940_DACLIM1 0x18
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#define WM8940_DACLIM2 0x19
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#define WM8940_ALC1 0x20
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#define WM8940_ALC2 0x21
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#define WM8940_ALC3 0x22
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#define WM8940_NOISEGATE 0x23
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#define WM8940_PLLN 0x24
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#define WM8940_PLLK1 0x25
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#define WM8940_PLLK2 0x26
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#define WM8940_PLLK3 0x27
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#define WM8940_ALC4 0x2A
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#define WM8940_INPUTCTL 0x2C
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#define WM8940_PGAGAIN 0x2D
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#define WM8940_ADCBOOST 0x2F
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#define WM8940_OUTPUTCTL 0x31
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#define WM8940_SPKMIX 0x32
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#define WM8940_SPKVOL 0x36
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#define WM8940_MONOMIX 0x38
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#define WM8940_CACHEREGNUM 0x57
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/* Clock divider Id's */
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#define WM8940_BCLKDIV 0
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#define WM8940_MCLKDIV 1
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#define WM8940_OPCLKDIV 2
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/* MCLK clock dividers */
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#define WM8940_MCLKDIV_1 0
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#define WM8940_MCLKDIV_1_5 1
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#define WM8940_MCLKDIV_2 2
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#define WM8940_MCLKDIV_3 3
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#define WM8940_MCLKDIV_4 4
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#define WM8940_MCLKDIV_6 5
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#define WM8940_MCLKDIV_8 6
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#define WM8940_MCLKDIV_12 7
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/* BCLK clock dividers */
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#define WM8940_BCLKDIV_1 0
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#define WM8940_BCLKDIV_2 1
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#define WM8940_BCLKDIV_4 2
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#define WM8940_BCLKDIV_8 3
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#define WM8940_BCLKDIV_16 4
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#define WM8940_BCLKDIV_32 5
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/* PLL Out Dividers */
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#define WM8940_OPCLKDIV_1 0
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#define WM8940_OPCLKDIV_2 1
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#define WM8940_OPCLKDIV_3 2
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#define WM8940_OPCLKDIV_4 3
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#endif /* _WM8940_H */
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