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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8e522e1d32
Commit:ca22312dc8("x86/platform/intel-mid: Extend PWRMU to support Penwell") ... enabled the PWRMU driver on platforms based on Intel Penwell, but unfortunately this is not enough. Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the future add a comment to both drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Fixes:ca22312dc8("x86/platform/intel-mid: Extend PWRMU to support Penwell") Link: http://lkml.kernel.org/r/20160908103232.137587-1-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/*
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* Intel MID platform PM support
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*
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* Copyright (C) 2016, Intel Corporation
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*
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/intel-mid.h>
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#include "pci.h"
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static bool mid_pci_power_manageable(struct pci_dev *dev)
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{
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return true;
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}
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static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
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{
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return intel_mid_pci_set_power_state(pdev, state);
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}
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static pci_power_t mid_pci_choose_state(struct pci_dev *pdev)
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{
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return PCI_D3hot;
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}
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static int mid_pci_sleep_wake(struct pci_dev *dev, bool enable)
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{
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return 0;
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}
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static int mid_pci_run_wake(struct pci_dev *dev, bool enable)
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{
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return 0;
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}
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static bool mid_pci_need_resume(struct pci_dev *dev)
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{
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return false;
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}
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static struct pci_platform_pm_ops mid_pci_platform_pm = {
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.is_manageable = mid_pci_power_manageable,
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.set_state = mid_pci_set_power_state,
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.choose_state = mid_pci_choose_state,
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.sleep_wake = mid_pci_sleep_wake,
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.run_wake = mid_pci_run_wake,
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.need_resume = mid_pci_need_resume,
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};
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#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
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/*
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* This table should be in sync with the one in
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* arch/x86/platform/intel-mid/pwr.c.
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*/
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static const struct x86_cpu_id lpss_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_PENWELL),
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
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{}
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};
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static int __init mid_pci_init(void)
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{
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const struct x86_cpu_id *id;
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id = x86_match_cpu(lpss_cpu_ids);
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if (id)
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pci_set_platform_pm(&mid_pci_platform_pm);
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return 0;
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}
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arch_initcall(mid_pci_init);
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