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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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59c82d12aa
Rework the r8a66597-udc fifo code to avoid unaligned accesses. Without this patch unaligned exceptions will degrade the USB performance. The exceptions come from the fact that the usb fifo data buffers may be misaligned. This patch updates the fifo access code to only use insl()/outsl() and insw()/outsw() in the case of properly aligned data buffers. The fallback case is that inl()/inw() are used for misaligned buffer reads together with outb() that is used for misaligned buffer writes. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
276 lines
6.7 KiB
C
276 lines
6.7 KiB
C
/*
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* R8A66597 UDC
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*
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* Copyright (C) 2007-2009 Renesas Solutions Corp.
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*
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* Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifndef __R8A66597_H__
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#define __R8A66597_H__
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#ifdef CONFIG_HAVE_CLK
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#include <linux/clk.h>
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#endif
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#include <linux/usb/r8a66597.h>
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#define R8A66597_MAX_SAMPLING 10
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#define R8A66597_MAX_NUM_PIPE 8
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#define R8A66597_MAX_NUM_BULK 3
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#define R8A66597_MAX_NUM_ISOC 2
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#define R8A66597_MAX_NUM_INT 2
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#define R8A66597_BASE_PIPENUM_BULK 3
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#define R8A66597_BASE_PIPENUM_ISOC 1
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#define R8A66597_BASE_PIPENUM_INT 6
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#define R8A66597_BASE_BUFNUM 6
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#define R8A66597_MAX_BUFNUM 0x4F
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#define is_bulk_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
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(pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
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#define is_interrupt_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
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(pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
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#define is_isoc_pipe(pipenum) \
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((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
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(pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
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struct r8a66597_pipe_info {
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u16 pipe;
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u16 epnum;
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u16 maxpacket;
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u16 type;
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u16 interval;
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u16 dir_in;
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};
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struct r8a66597_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct r8a66597_ep {
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struct usb_ep ep;
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struct r8a66597 *r8a66597;
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struct list_head queue;
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unsigned busy:1;
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unsigned wedge:1;
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unsigned internal_ccpl:1; /* use only control */
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/* this member can able to after r8a66597_enable */
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unsigned use_dma:1;
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u16 pipenum;
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u16 type;
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const struct usb_endpoint_descriptor *desc;
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/* register address */
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unsigned char fifoaddr;
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unsigned char fifosel;
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unsigned char fifoctr;
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unsigned char fifotrn;
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unsigned char pipectr;
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};
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struct r8a66597 {
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spinlock_t lock;
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unsigned long reg;
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#ifdef CONFIG_HAVE_CLK
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struct clk *clk;
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#endif
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struct r8a66597_platdata *pdata;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
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struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
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struct r8a66597_ep *epaddr2ep[16];
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struct timer_list timer;
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struct usb_request *ep0_req; /* for internal request */
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u16 ep0_data; /* for internal request */
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u16 old_vbus;
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u16 scount;
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u16 old_dvsq;
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/* pipe config */
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unsigned char bulk;
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unsigned char interrupt;
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unsigned char isochronous;
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unsigned char num_dma;
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unsigned irq_sense_low:1;
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};
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#define gadget_to_r8a66597(_gadget) \
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container_of(_gadget, struct r8a66597, gadget)
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#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
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static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
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{
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return inw(r8a66597->reg + offset);
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}
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static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
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unsigned long offset,
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unsigned char *buf,
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int len)
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{
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unsigned long fifoaddr = r8a66597->reg + offset;
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unsigned int data;
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int i;
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if (r8a66597->pdata->on_chip) {
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/* 32-bit accesses for on_chip controllers */
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/* aligned buf case */
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if (len >= 4 && !((unsigned long)buf & 0x03)) {
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insl(fifoaddr, buf, len / 4);
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buf += len & ~0x03;
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len &= 0x03;
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}
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/* unaligned buf case */
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for (i = 0; i < len; i++) {
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if (!(i & 0x03))
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data = inl(fifoaddr);
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buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
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}
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} else {
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/* 16-bit accesses for external controllers */
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/* aligned buf case */
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if (len >= 2 && !((unsigned long)buf & 0x01)) {
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insw(fifoaddr, buf, len / 2);
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buf += len & ~0x01;
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len &= 0x01;
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}
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/* unaligned buf case */
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for (i = 0; i < len; i++) {
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if (!(i & 0x01))
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data = inw(fifoaddr);
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buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
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}
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}
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}
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static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
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unsigned long offset)
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{
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outw(val, r8a66597->reg + offset);
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}
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static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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unsigned long offset,
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unsigned char *buf,
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int len)
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{
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unsigned long fifoaddr = r8a66597->reg + offset;
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int adj = 0;
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int i;
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if (r8a66597->pdata->on_chip) {
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/* 32-bit access only if buf is 32-bit aligned */
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if (len >= 4 && !((unsigned long)buf & 0x03)) {
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outsl(fifoaddr, buf, len / 4);
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buf += len & ~0x03;
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len &= 0x03;
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}
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} else {
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/* 16-bit access only if buf is 16-bit aligned */
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if (len >= 2 && !((unsigned long)buf & 0x01)) {
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outsw(fifoaddr, buf, len / 2);
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buf += len & ~0x01;
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len &= 0x01;
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}
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}
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/* adjust fifo address in the little endian case */
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if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
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if (r8a66597->pdata->on_chip)
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adj = 0x03; /* 32-bit wide */
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else
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adj = 0x01; /* 16-bit wide */
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}
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for (i = 0; i < len; i++)
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outb(buf[i], fifoaddr + adj - (i & adj));
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}
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static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
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u16 val, u16 pat, unsigned long offset)
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{
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u16 tmp;
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tmp = r8a66597_read(r8a66597, offset);
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tmp = tmp & (~pat);
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tmp = tmp | val;
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r8a66597_write(r8a66597, tmp, offset);
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}
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static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
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{
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u16 clock = 0;
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switch (pdata->xtal) {
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case R8A66597_PLATDATA_XTAL_12MHZ:
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clock = XTAL12;
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break;
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case R8A66597_PLATDATA_XTAL_24MHZ:
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clock = XTAL24;
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break;
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case R8A66597_PLATDATA_XTAL_48MHZ:
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clock = XTAL48;
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break;
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default:
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printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
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break;
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}
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return clock;
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}
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#define r8a66597_bclr(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, 0, val, offset)
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#define r8a66597_bset(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, val, 0, offset)
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#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
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#define enable_irq_ready(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define disable_irq_ready(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define enable_irq_empty(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define disable_irq_empty(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define enable_irq_nrdy(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#define disable_irq_nrdy(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#endif /* __R8A66597_H__ */
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