mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 03:26:40 +07:00
6c355fafeb
Added Intel Braswell CPU id for SOC DTS. Since this doesn't support APIC IRQ, the driver is modified to have capability to not register any modifiable trips. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
496 lines
11 KiB
C
496 lines
11 KiB
C
/*
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* intel_soc_dts_thermal.c
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/thermal.h>
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#include <asm/cpu_device_id.h>
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#include <asm/iosf_mbi.h>
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#define SOC_DTS_OFFSET_ENABLE 0xB0
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#define SOC_DTS_OFFSET_TEMP 0xB1
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#define SOC_DTS_OFFSET_PTPS 0xB2
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#define SOC_DTS_OFFSET_PTTS 0xB3
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#define SOC_DTS_OFFSET_PTTSS 0xB4
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#define SOC_DTS_OFFSET_PTMC 0x80
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#define SOC_DTS_TE_AUX0 0xB5
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#define SOC_DTS_TE_AUX1 0xB6
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#define SOC_DTS_AUX0_ENABLE_BIT BIT(0)
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#define SOC_DTS_AUX1_ENABLE_BIT BIT(1)
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#define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16)
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#define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17)
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#define SOC_DTS_TE_SCI_ENABLE BIT(9)
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#define SOC_DTS_TE_SMI_ENABLE BIT(10)
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#define SOC_DTS_TE_MSI_ENABLE BIT(11)
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#define SOC_DTS_TE_APICA_ENABLE BIT(14)
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#define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4)
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/* DTS encoding for TJ MAX temperature */
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#define SOC_DTS_TJMAX_ENCODING 0x7F
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/* IRQ 86 is a fixed APIC interrupt for BYT DTS Aux threshold notifications */
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#define BYT_SOC_DTS_APIC_IRQ 86
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/* Only 2 out of 4 is allowed for OSPM */
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#define SOC_MAX_DTS_TRIPS 2
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/* Mask for two trips in status bits */
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#define SOC_DTS_TRIP_MASK 0x03
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/* DTS0 and DTS 1 */
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#define SOC_MAX_DTS_SENSORS 2
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#define CRITICAL_OFFSET_FROM_TJ_MAX 5000
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struct soc_sensor_entry {
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int id;
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u32 tj_max;
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u32 temp_mask;
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u32 temp_shift;
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u32 store_status;
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struct thermal_zone_device *tzone;
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};
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static struct soc_sensor_entry *soc_dts[SOC_MAX_DTS_SENSORS];
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static int crit_offset = CRITICAL_OFFSET_FROM_TJ_MAX;
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module_param(crit_offset, int, 0644);
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MODULE_PARM_DESC(crit_offset,
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"Critical Temperature offset from tj max in millidegree Celsius.");
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static DEFINE_MUTEX(aux_update_mutex);
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static spinlock_t intr_notify_lock;
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static int soc_dts_thres_irq;
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static int get_tj_max(u32 *tj_max)
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{
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u32 eax, edx;
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u32 val;
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int err;
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (err)
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goto err_ret;
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else {
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val = (eax >> 16) & 0xff;
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if (val)
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*tj_max = val * 1000;
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else {
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err = -EINVAL;
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goto err_ret;
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}
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}
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return 0;
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err_ret:
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*tj_max = 0;
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return err;
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}
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static int sys_get_trip_temp(struct thermal_zone_device *tzd,
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int trip, unsigned long *temp)
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{
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int status;
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u32 out;
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struct soc_sensor_entry *aux_entry;
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aux_entry = tzd->devdata;
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if (!trip) {
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/* Just return the critical temp */
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*temp = aux_entry->tj_max - crit_offset;
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return 0;
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}
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mutex_lock(&aux_update_mutex);
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_PTPS, &out);
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mutex_unlock(&aux_update_mutex);
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if (status)
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return status;
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out = (out >> (trip * 8)) & SOC_DTS_TJMAX_ENCODING;
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if (!out)
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*temp = 0;
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else
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*temp = aux_entry->tj_max - out * 1000;
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return 0;
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}
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static int update_trip_temp(struct soc_sensor_entry *aux_entry,
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int thres_index, unsigned long temp)
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{
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int status;
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u32 temp_out;
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u32 out;
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u32 store_ptps;
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u32 store_ptmc;
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u32 store_te_out;
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u32 te_out;
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u32 int_enable_bit = SOC_DTS_TE_APICA_ENABLE |
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SOC_DTS_TE_MSI_ENABLE;
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temp_out = (aux_entry->tj_max - temp) / 1000;
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_PTPS, &store_ptps);
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if (status)
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return status;
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out = (store_ptps & ~(0xFF << (thres_index * 8)));
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out |= (temp_out & 0xFF) << (thres_index * 8);
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status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTPS, out);
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if (status)
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return status;
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pr_debug("update_trip_temp PTPS = %x\n", out);
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_PTMC, &out);
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if (status)
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goto err_restore_ptps;
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store_ptmc = out;
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_TE_AUX0 + thres_index,
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&te_out);
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if (status)
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goto err_restore_ptmc;
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store_te_out = te_out;
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/* Enable for CPU module 0 and module 1 */
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out |= (SOC_DTS_CPU_MODULE0_ENABLE_BIT |
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SOC_DTS_CPU_MODULE1_ENABLE_BIT);
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if (temp) {
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if (thres_index)
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out |= SOC_DTS_AUX1_ENABLE_BIT;
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else
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out |= SOC_DTS_AUX0_ENABLE_BIT;
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te_out |= int_enable_bit;
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} else {
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if (thres_index)
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out &= ~SOC_DTS_AUX1_ENABLE_BIT;
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else
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out &= ~SOC_DTS_AUX0_ENABLE_BIT;
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te_out &= ~int_enable_bit;
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}
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status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTMC, out);
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if (status)
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goto err_restore_te_out;
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status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_TE_AUX0 + thres_index,
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te_out);
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if (status)
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goto err_restore_te_out;
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return 0;
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err_restore_te_out:
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iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTMC, store_te_out);
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err_restore_ptmc:
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iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTMC, store_ptmc);
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err_restore_ptps:
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iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTPS, store_ptps);
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/* Nothing we can do if restore fails */
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return status;
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}
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static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
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unsigned long temp)
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{
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struct soc_sensor_entry *aux_entry = tzd->devdata;
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int status;
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if (temp > (aux_entry->tj_max - crit_offset))
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return -EINVAL;
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mutex_lock(&aux_update_mutex);
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status = update_trip_temp(tzd->devdata, trip, temp);
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mutex_unlock(&aux_update_mutex);
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return status;
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}
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static int sys_get_trip_type(struct thermal_zone_device *thermal,
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int trip, enum thermal_trip_type *type)
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{
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if (trip)
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*type = THERMAL_TRIP_PASSIVE;
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else
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*type = THERMAL_TRIP_CRITICAL;
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return 0;
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}
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static int sys_get_curr_temp(struct thermal_zone_device *tzd,
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unsigned long *temp)
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{
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int status;
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u32 out;
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struct soc_sensor_entry *aux_entry;
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aux_entry = tzd->devdata;
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_TEMP, &out);
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if (status)
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return status;
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out = (out & aux_entry->temp_mask) >> aux_entry->temp_shift;
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out -= SOC_DTS_TJMAX_ENCODING;
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*temp = aux_entry->tj_max - out * 1000;
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return 0;
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}
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static struct thermal_zone_device_ops tzone_ops = {
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.get_temp = sys_get_curr_temp,
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.get_trip_temp = sys_get_trip_temp,
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.get_trip_type = sys_get_trip_type,
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.set_trip_temp = sys_set_trip_temp,
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};
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static void free_soc_dts(struct soc_sensor_entry *aux_entry)
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{
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if (aux_entry) {
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iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_ENABLE, aux_entry->store_status);
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thermal_zone_device_unregister(aux_entry->tzone);
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kfree(aux_entry);
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}
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}
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static int soc_dts_enable(int id)
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{
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u32 out;
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int ret;
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ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_ENABLE, &out);
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if (ret)
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return ret;
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if (!(out & BIT(id))) {
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out |= BIT(id);
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ret = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_ENABLE, out);
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if (ret)
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return ret;
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}
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return ret;
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}
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static struct soc_sensor_entry *alloc_soc_dts(int id, u32 tj_max,
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bool notification_support)
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{
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struct soc_sensor_entry *aux_entry;
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char name[10];
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int trip_count = 0;
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int trip_mask = 0;
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int err;
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aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
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if (!aux_entry) {
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err = -ENOMEM;
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return ERR_PTR(-ENOMEM);
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}
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/* Store status to restor on exit */
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err = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_ENABLE,
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&aux_entry->store_status);
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if (err)
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goto err_ret;
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aux_entry->id = id;
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aux_entry->tj_max = tj_max;
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aux_entry->temp_mask = 0x00FF << (id * 8);
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aux_entry->temp_shift = id * 8;
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if (notification_support) {
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trip_count = SOC_MAX_DTS_TRIPS;
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trip_mask = 0x02;
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}
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snprintf(name, sizeof(name), "soc_dts%d", id);
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aux_entry->tzone = thermal_zone_device_register(name,
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trip_count,
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trip_mask,
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aux_entry, &tzone_ops,
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NULL, 0, 0);
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if (IS_ERR(aux_entry->tzone)) {
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err = PTR_ERR(aux_entry->tzone);
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goto err_ret;
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}
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err = soc_dts_enable(id);
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if (err)
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goto err_aux_status;
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return aux_entry;
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err_aux_status:
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thermal_zone_device_unregister(aux_entry->tzone);
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err_ret:
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kfree(aux_entry);
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return ERR_PTR(err);
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}
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static void proc_thermal_interrupt(void)
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{
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u32 sticky_out;
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int status;
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u32 ptmc_out;
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unsigned long flags;
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spin_lock_irqsave(&intr_notify_lock, flags);
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/* Clear APIC interrupt */
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_PTMC, &ptmc_out);
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ptmc_out |= SOC_DTS_PTMC_APIC_DEASSERT_BIT;
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status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTMC, ptmc_out);
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/* Read status here */
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status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
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SOC_DTS_OFFSET_PTTSS, &sticky_out);
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pr_debug("status %d PTTSS %x\n", status, sticky_out);
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if (sticky_out & SOC_DTS_TRIP_MASK) {
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int i;
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/* reset sticky bit */
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status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
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SOC_DTS_OFFSET_PTTSS, sticky_out);
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spin_unlock_irqrestore(&intr_notify_lock, flags);
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for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
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pr_debug("TZD update for zone %d\n", i);
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thermal_zone_device_update(soc_dts[i]->tzone);
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}
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} else
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spin_unlock_irqrestore(&intr_notify_lock, flags);
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}
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static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
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{
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proc_thermal_interrupt();
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pr_debug("proc_thermal_interrupt\n");
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return IRQ_HANDLED;
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}
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static const struct x86_cpu_id soc_thermal_ids[] = {
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{ X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x37, 0, BYT_SOC_DTS_APIC_IRQ},
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{ X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x4c, 0, 0},
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
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static int __init intel_soc_thermal_init(void)
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{
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u32 tj_max;
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int err = 0;
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int i;
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const struct x86_cpu_id *match_cpu;
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match_cpu = x86_match_cpu(soc_thermal_ids);
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if (!match_cpu)
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return -ENODEV;
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if (get_tj_max(&tj_max))
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return -EINVAL;
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soc_dts_thres_irq = (int)match_cpu->driver_data;
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for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
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soc_dts[i] = alloc_soc_dts(i, tj_max,
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soc_dts_thres_irq ? true : false);
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if (IS_ERR(soc_dts[i])) {
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err = PTR_ERR(soc_dts[i]);
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goto err_free;
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}
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}
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spin_lock_init(&intr_notify_lock);
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if (soc_dts_thres_irq) {
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err = request_threaded_irq(soc_dts_thres_irq, NULL,
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soc_irq_thread_fn,
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IRQF_TRIGGER_RISING | IRQF_ONESHOT,
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"soc_dts", soc_dts);
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if (err) {
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pr_err("request_threaded_irq ret %d\n", err);
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goto err_free;
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}
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}
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for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
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err = update_trip_temp(soc_dts[i], 0, tj_max - crit_offset);
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if (err)
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goto err_trip_temp;
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}
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return 0;
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err_trip_temp:
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i = SOC_MAX_DTS_SENSORS;
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if (soc_dts_thres_irq)
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free_irq(soc_dts_thres_irq, soc_dts);
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err_free:
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while (--i >= 0)
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free_soc_dts(soc_dts[i]);
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return err;
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}
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static void __exit intel_soc_thermal_exit(void)
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{
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int i;
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for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
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update_trip_temp(soc_dts[i], 0, 0);
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if (soc_dts_thres_irq)
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free_irq(soc_dts_thres_irq, soc_dts);
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for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
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free_soc_dts(soc_dts[i]);
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}
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module_init(intel_soc_thermal_init)
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module_exit(intel_soc_thermal_exit)
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MODULE_DESCRIPTION("Intel SoC DTS Thermal Driver");
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MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
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MODULE_LICENSE("GPL v2");
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