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fe31edc8a3
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: "David S. Miller" <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
169 lines
4.7 KiB
C
169 lines
4.7 KiB
C
/*
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* IDE tuning and bus mastering support for the CS5510/CS5520
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* chipsets
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*
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* The CS5510/CS5520 are slightly unusual devices. Unlike the
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* typical IDE controllers they do bus mastering with the drive in
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* PIO mode and smarter silicon.
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*
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* The practical upshot of this is that we must always tune the
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* drive for the right PIO mode. We must also ignore all the blacklists
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* and the drive bus mastering DMA information.
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*
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* *** This driver is strictly experimental ***
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*
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* (c) Copyright Red Hat Inc 2002
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* For the avoidance of doubt the "preferred form" of this code is one which
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* is in an open non patent encumbered format. Where cryptographic key signing
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* forms part of the process of creating an executable the information
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* including keys needed to generate an equivalently functional executable
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* are deemed to be part of the source code.
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/dma-mapping.h>
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#define DRV_NAME "cs5520"
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struct pio_clocks
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{
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int address;
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int assert;
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int recovery;
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};
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static struct pio_clocks cs5520_pio_clocks[]={
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{3, 6, 11},
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{2, 5, 6},
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{1, 4, 3},
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{1, 3, 2},
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{1, 2, 1}
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};
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static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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int controller = drive->dn > 1 ? 1 : 0;
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const u8 pio = drive->pio_mode - XFER_PIO_0;
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/* 8bit CAT/CRT - 8bit command timing for channel */
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pci_write_config_byte(pdev, 0x62 + controller,
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
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/* FIXME: should these use address ? */
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/* Data read timing */
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pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* Write command timing */
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pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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}
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static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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printk(KERN_ERR "cs55x0: bad ide timing.\n");
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drive->pio_mode = XFER_PIO_0 + 0;
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cs5520_set_pio_mode(hwif, drive);
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}
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static const struct ide_port_ops cs5520_port_ops = {
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.set_pio_mode = cs5520_set_pio_mode,
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.set_dma_mode = cs5520_set_dma_mode,
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};
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static const struct ide_port_info cyrix_chipset = {
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.name = DRV_NAME,
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.enablebits = { { 0x60, 0x01, 0x01 }, { 0x60, 0x02, 0x02 } },
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.port_ops = &cs5520_port_ops,
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.host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
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.pio_mask = ATA_PIO4,
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};
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/*
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* The 5510/5520 are a bit weird. They don't quite set up the way
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* the PCI helper layer expects so we must do much of the set up
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* work longhand.
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*/
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static int cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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const struct ide_port_info *d = &cyrix_chipset;
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struct ide_hw hw[2], *hws[] = { NULL, NULL };
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ide_setup_pci_noise(dev, d);
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/* We must not grab the entire device, it has 'ISA' space in its
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* BARS too and we will freak out other bits of the kernel
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*/
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if (pci_enable_device_io(dev)) {
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printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
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return -ENODEV;
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}
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pci_set_master(dev);
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if (pci_set_dma_mask(dev, DMA_BIT_MASK(32))) {
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printk(KERN_WARNING "%s: No suitable DMA available.\n",
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d->name);
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return -ENODEV;
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}
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/*
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* Now the chipset is configured we can let the core
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* do all the device setup for us
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*/
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ide_pci_setup_ports(dev, d, &hw[0], &hws[0]);
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hw[0].irq = 14;
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hw[1].irq = 15;
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return ide_host_add(d, hws, 2, NULL);
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}
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static const struct pci_device_id cs5520_pci_tbl[] = {
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
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static struct pci_driver cs5520_pci_driver = {
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.name = "Cyrix_IDE",
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.id_table = cs5520_pci_tbl,
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.probe = cs5520_init_one,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init cs5520_ide_init(void)
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{
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return ide_pci_register_driver(&cs5520_pci_driver);
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}
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module_init(cs5520_ide_init);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
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MODULE_LICENSE("GPL");
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